IP Library Granted Patent US 11,502,703
Granted Patent B2
US 11,502,703 · App. 16/879,492 · Granted Nov 15, 2022

Descrambler for memory systems and method thereof

Inventors: Fan Zhang (Fremont, CA); Aman Bhatia (Los Gatos, CA); Xuanxuan Lu (San Jose, CA); Haobo Wang (San Jose, CA); Meysam Asadi (Fremont, CA)
Assignee: SK hynix Inc.
H03M13/1102G06F11/1012H03M13/116H03M13/1177H03M13/1575G06F2212/1036G06F2212/7211
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Quick Facts
Patent No.
US 11,502,703
App. No.
16/879,492
Granted
Nov 15, 2022
Kind
B2
Abstract

A descrambler receives data from a memory device. The descrambler calculates a sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences. The descrambler selects a sub-syndrome weight among the multiple sub-syndrome weights. The descrambler determines, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences.

Claims (34)

1. A memory system comprising:

a memory device; and

a controller including a descrambler, which is coupled to the memory device and suitable for:

receiving data from the memory device;

descrambling the data, using each of a plurality of scrambler sequences, to generate a corresponding plurality of descrambled sequences;

calculating a sub-syndrome weight for multiple bits in each of the corresponding plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences;

selecting a sub-syndrome weight among the multiple sub-syndrome weights of the corresponding plurality of descrambled sequences; and

determining, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences,

wherein the descrambler calculates the sub-syndrome weight for the multiple bits in each of the plurality of descrambled sequences using a subset circulant matrix in a set parity check matrix,

and

wherein the multiple bits are the last nq bits in each of the plurality of descrambled sequences and the subset circulant matrix is a (mq×nq) matrix having a circulant size of (q×q) in the set parity check matrix, where m and n are integers greater than 1.

2. The memory system of claim 1 , wherein the parity check matrix is a parity check matrix for a low density parity check (LDPC) code.

3. The memory system of claim 1 , wherein the descrambler selects the lowest sub-syndrome weight among the multiple sub-syndrome weights.

4. The memory system of claim 1 , wherein the descrambler compares each of the multiple sub-syndrome weights with a threshold value and selects a sub-syndrome weight less than the threshold value among the sub-syndrome weights.

5. The memory system of claim 1 , wherein the data received from the memory system comprises randomized data.

6. The memory system of claim 5 , wherein the randomized data has a minimized number of sequential bits of different values.

7. A method for operating a memory system, which includes a memory device and a controller including a descrambler coupled to the memory device, the method comprising:

receiving data from the memory device;

descrambling the data, using each of a plurality of scrambler sequences, to generate a corresponding plurality of descrambled sequences;

calculating a sub-syndrome weight for multiple bits in each of the corresponding plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences;

selecting a sub-syndrome weight among the multiple sub-syndrome weights of the corresponding plurality of descrambled sequences; and

determining, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences,

wherein the calculating of the sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences comprises:

calculating the sub-syndrome weight for the multiple bits in each of the plurality of descrambled sequences using a subset circulant matrix in a set parity check matrix,

and

wherein the multiple bits are the last nq bits in each of the plurality of descrambled sequences and the subset circulant matrix is a (mq×nq) matrix having a circulant size of (q×q) in the set parity check matrix, where m and n are integers greater than 1.

8. The method of claim 7 , wherein the parity check matrix is a parity check matrix for a low density parity check (LDPC) code.

9. The method of claim 7 , wherein the selecting of the sub-syndrome weight among the multiple sub-syndrome weights comprises:

selecting the lowest sub-syndrome weight among the multiple sub-syndrome weights.

10. The method of claim 7 , wherein the selecting of the sub-syndrome weight among the multiple sub-syndrome weights comprises:

comparing each of the multiple sub-syndrome weights with a threshold value; and

selecting a sub-syndrome weight less than the threshold value among the sub-syndrome weights.

11. The method of claim 7 , wherein the data received from the memory system comprises randomized data.

12. The method of claim 11 , wherein the randomized data has a minimized number of sequential bits of different values.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2021
From: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
To: SK HYNIX INC.
Reel/Frame 056883/0151 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2020
From: ZHANG, FAN; BHATIA, AMAN; LU, XUANXUAN; WANG, HAOBO; ASADI, MEYSAM
To: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
Reel/Frame 052716/0830 →
Continuity (1)
Related Publication 20210367616A1 · Nov 25, 2021
Cited By (1)
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