Expanded host domains in PCIe systems
Computing architectures, platforms, and systems are provided herein. In one example, a system is provided. The system includes a communication arrangement for peripheral component interconnect express (PCIe) traffic transferred over a communication fabric. The communication arrangement establishes an expanded address that provides a quantity of port identifiers to a host greater than indicated by a quantity of bits in a port field of the PCIe traffic, where the expanded address employs one or more bits of the PCIe traffic other than the port field. The communication arrangement detects a transfer among the PCIe traffic issued by the host having the expanded address corresponding to a destination. Based on the expanded address, the communication arrangement identifies routing information to route the transfer over the communication fabric to the destination.
1. A system comprising:
a communication arrangement for peripheral component interconnect express (PCIe) traffic transferred over a communication fabric;
wherein the communication arrangement is configured to:
establish an expanded address that provides a quantity of port identifiers to a host greater than indicated by a quantity of bits in a port field of the PCIe traffic, wherein the expanded address employs one or more bits of the PCIe traffic other than the port field;
detect a transfer among the PCIe traffic issued by the host having the expanded address corresponding to a destination; and
based on the expanded address, identify routing information to route the transfer over the communication fabric to the destination.
2. The system of claim 1 , wherein the one or more bits of the PCIe traffic correspond to one or more bits of a function field of the PCIe traffic.
3. The system of claim 2 , wherein the one or more bits of the function field of the PCIe traffic comprise one or more most significant bits of the function field of the PCIe traffic.
4. The system of claim 1 , wherein the communication arrangement is configured to route the transfer to the destination by at least identifying the routing information and clearing the one or more bits of the PCIe traffic before transfer to the destination.
5. The system of claim 1 , wherein the quantity of bits in the port field corresponds to a 256 endpoint device limit per host port, and wherein the quantity of port identifiers greater than indicated by the quantity of bits in the port field corresponds to a limit greater than 256 endpoint devices per host port.
6. The system of claim 1 , wherein responsive to detecting the transfer, the communication arrangement is configured to trap the transfer in the communication fabric and determine the routing information based at least on the one or more bits of the PCIe traffic for the transfer.
7. The system of claim 1 , wherein responsive to detecting the transfer, the communication arrangement is configured to indicate the one or more bits of the PCIe traffic to control circuitry configured to select between look up tables based at least on the one or more bits, and use a selected look up table to retrieve the routing information for the transfer to reach the destination over the communication fabric.
8. A method comprising:
establishing, for peripheral component interconnect express (PCIe) traffic transferred over a communication fabric, an expanded address that provides a quantity of port identifiers to a host greater than indicated by a quantity of bits in a port field of the PCIe traffic, wherein the expanded address employs one or more bits of the PCIe traffic other than the port field;
detecting a transfer among the PCIe traffic issued by the host having the expanded address corresponding to a destination; and
based on the expanded address, identifying routing information to route the transfer over the communication fabric to the destination.
9. The method of claim 8 , wherein the one or more bits of the PCIe traffic correspond to one or more bits of a function field of the PCIe traffic.
10. The method of claim 9 , wherein the one or more bits of the function field of the PCIe traffic comprise one or more most significant bits of the function field of the PCIe traffic.
11. The method of claim 8 , further comprising:
routing the transfer to the destination by at least identifying the routing information and clearing the one or more bits of the PCIe traffic before transfer to the destination.
12. The method of claim 8 , wherein the quantity of bits in the port field corresponds to a 256 endpoint device limit per host port, and wherein the quantity of port identifiers greater than indicated by the quantity of bits in the port field corresponds to a limit greater than 256 endpoint devices per host port.
13. The method of claim 8 , further comprising:
responsive to detecting the transfer, trapping the transfer in the communication fabric and determining the routing information based at least on the one or more bits of the PCIe traffic for the transfer.
14. The method of claim 8 , further comprising:
responsive to detecting the transfer, indicating the one or more bits of the PCIe traffic to control circuitry configured to select between look up tables based at least on the one or more bits, and using a selected look up table to retrieve the routing information for the transfer to reach the destination over the communication fabric.
15. An apparatus comprising:
one or more non-transitory computer readable storage media;
a processor operatively coupled with the one or more non-transitory computer readable storage media; and
program instructions stored on the one or more non-transitory computer readable storage media, that when executed by the host processor, direct the processor to at least:
establish, for peripheral component interconnect express (PCIe) traffic transferred over a communication fabric, an expanded address that provides a quantity of port identifiers to a host greater than indicated by a quantity of bits in a port field of the PCIe traffic, wherein the expanded address employs one or more bits of the PCIe traffic other than the port field;
detect a transfer among the PCIe traffic issued by the host having the expanded address corresponding to a destination; and
based on the expanded address, identify routing information to route the transfer over the communication fabric to the destination.
16. The apparatus of claim 15 , wherein the one or more bits of the PCIe traffic correspond to one or more bits of a function field of the PCIe traffic.
17. The apparatus of claim 15 , comprising program instructions that, when executed by the host processor, direct the processor to at least:
route the transfer to the destination by at least identifying the routing information and clearing the one or more bits of the PCIe traffic before transfer to the destination.
18. The apparatus of claim 15 , wherein the quantity of bits in the port field corresponds to a 256 endpoint device limit per host port, and wherein the quantity of port identifiers greater than indicated by the quantity of bits in the port field corresponds to a limit greater than 256 endpoint devices per host port.
19. The apparatus of claim 15 , comprising program instructions that, when executed by the host processor, direct the processor to at least:
responsive to detecting the transfer, trap the transfer in the communication fabric and determine the routing information based at least on the one or more bits of the PCIe traffic for the transfer.
20. The apparatus of claim 15 , comprising program instructions that, when executed by the host processor, direct the processor to at least:
responsive to detecting the transfer, indicate the one or more bits of the PCIe traffic to control circuitry configured to select between look up tables based at least on the one or more bits, and use a selected look up table to retrieve the routing information for the transfer to reach the destination over the communication fabric.