Integrated circuit with backside power rail and backside interconnect

1. An integrated circuit comprising:

a first layer including a first metal rail;

a second layer including a second metal rail, the second layer above the first layer along a first direction;

a third layer including an active region of a transistor, the third layer above the second layer along the first direction, the active region coupled to the second metal rail through a via contact between the second metal rail and the active region;

a fourth layer including a third metal rail, the fourth layer above the third layer along the first direction; and

a fifth layer including a fourth metal rail, the fifth layer above the fourth layer along the first direction.

2. The integrated circuit of claim 1 , wherein the first metal rail is to provide a supply voltage to the active region of the transistor through the second metal rail.

3. The integrated circuit of claim 1 , wherein the third metal rail is to provide an electrical signal from or to the transistor.

4. The integrated circuit of claim 1 , wherein the first metal rail is electrically coupled to the second metal rail through another via contact.

5. The integrated circuit of claim 1 , wherein the third metal rail is directly coupled to a second side of the active region of the transistor.

6. The integrated circuit of claim 5 , wherein the fourth layer includes:

a fifth metal rail directly coupled to another active region of the transistor.

7. The integrated circuit of claim 6 ,

wherein the third metal rail extends in a second direction perpendicular to the first direction, wherein the third metal rail includes a first end and a second end, and

wherein the fifth metal rail extends in the second direction, wherein the fifth metal rail includes a third end and a fourth end, wherein the first end of the third metal rail and the third end of the fifth metal rail are aligned, wherein the second end of the third metal rail and the fourth end of the fifth metal rail are aligned.

8. The integrated circuit of claim 7 , wherein the second layer includes:

a sixth metal rail coupled to the another active region of the transistor.

9. The integrated circuit of claim 8 , wherein the sixth metal rail is coupled to an active region of another transistor.

10. The integrated circuit of claim 9 , further comprising:

a seventh metal rail of the transistor extending in the second direction, the seventh metal rail disposed between the active region of the transistor and the another active region of the transistor, the seventh metal rail partially overlapping the sixth metal rail.

11. The integrated circuit of claim 1 , wherein the fourth metal rail extends in a second direction perpendicular to the first direction, wherein the first metal rail extends in the second direction.

12. The integrated circuit of claim 11 , wherein the second metal rail extends in a third direction, the first direction normal to the second direction and the third direction.

13. The integrated circuit of claim 11 , wherein the second metal rail extends in the second direction.

14. The integrated circuit of claim 1 , further comprising:

a sixth layer including a fifth metal rail between the first layer and the second layer, the second metal rail extending in a second direction, the fifth metal rail extending in a third direction, the first direction normal to the second direction and the third direction.

15. A method of forming an integrated circuit, the method comprising:

forming a first layer including a first metal rail;

forming a second layer including a second metal rail, the second layer above the first layer along a first direction;

forming a via contact above the second metal rail along the first direction;

forming a third layer including an active region of a transistor, the third layer above the second layer along the first direction, the via contact to electrically couple between the active region and the second metal rail;

forming a fourth layer including a third metal rail, the fourth layer above the third layer along the first direction; and

forming a fifth layer including a fourth metal rail, the fifth layer above the fourth layer along the first direction.

16. The method of claim 15 , wherein the first metal rail is to provide a supply voltage to the active region of the transistor through the second metal rail, wherein the third metal rail is to provide an electrical signal from or to the transistor.

17. The method of claim 15 , further comprising:

forming another via contact to electrically couple the first metal rail to the second metal rail.

18. An integrated circuit comprising:

a first layer including an active region of a transistor;

a second layer including a first metal rail directly coupled to a first side of the active region of the transistor, the second layer above the first layer along a first direction;

a third layer including a second metal rail coupled to a second side of the active region of the transistor through a first via contact between the second side of the active region and the second metal rail, the second side facing away from the first side, the first layer above the third layer along the first direction; and

a fourth layer including a third metal rail coupled to the second metal rail through a second via contact, the third layer above the fourth layer along the first direction.

19. The integrated circuit of claim 18 , further comprising:

another active region of the transistor;

wherein the second layer includes a fourth metal rail directly coupled to a first side of the another active region of the transistor; and

wherein the third layer includes a fifth metal rail coupled to a second side of the another active region of the transistor through a third via contact.

20. The integrated circuit of claim 19 , wherein the third metal rail is to provide a supply voltage to the active region of the transistor through the second metal rail, wherein the fifth metal rail is to provide an electrical signal to or from the another active region of the transistor.