Vertical memory device with support layer
A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.
1. A vertical memory device comprising:
gate electrode structures each including gate electrodes spaced apart from one another on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, wherein each of the gate electrodes extends in a second direction substantially parallel to the upper surface of the substrate, and the gate electrode structures are spaced apart from one another in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction;
channels each extending through one of the gate electrode structures in the first direction;
a first division pattern extending in the second direction between first ones of the gate electrode structures neighboring in the third direction;
second and third division patterns alternately disposed in the second direction between second ones of the gate electrode structures neighboring in the third direction; and
a support layer on the gate electrode structures, wherein the support layer is at substantially the same height as upper portions of the first and second division patterns and contacting the upper portions of the first and second division patterns,
wherein the upper portions of the first division pattern are spaced apart from one another in the second direction; and
wherein the upper portions of the first division patterns and the upper portions of the second division patterns are arranged in a zigzag pattern in the second direction in a plan view.
2. The vertical memory device of claim 1 , wherein each of the upper portions of the first division patterns partially overlaps the upper portions of the second division patterns in the third direction.
3. The vertical memory device of claim 1 , wherein the first division pattern is one of a plurality of first division patterns spaced apart from one another in the third direction, and
wherein the second division pattern is disposed between neighboring first division patterns of the plurality of first division patterns neighboring in the third direction.
4. The vertical memory device of claim 3 , wherein the second division pattern is one of a plurality of second division patterns spaced apart from one another in the third direction between the neighboring first division patterns.
5. The vertical memory device of claim 1 , wherein the first division pattern includes a lower portion extending in the second direction, and
wherein each of the upper portions of the first division pattern contact an upper surface of the lower portion of the first division pattern.
6. The vertical memory device of claim 5 , wherein a width in the third direction of each of the upper portions of the first division pattern is greater than that of the lower portion thereof.
7. The vertical memory device of claim 5 , wherein a distance of the upper surface of the lower portion of the first division pattern from the substrate is greater than a distance of an upper surface of the third division pattern from the substrate.
8. The vertical memory device of claim 5 , further comprising a metal oxide pattern covering a sidewall of each of the upper portions of the first division pattern.
9. The vertical memory device of claim 8 , further comprising a blocking pattern covering lower and upper surfaces and a sidewall of each of the gate electrodes,
wherein the blocking pattern includes a material substantially the same as that of the metal oxide pattern.
10. The vertical memory device of claim 1 , wherein the second division pattern includes lower portions spaced apart from one another in the second direction and connected to the third division patterns, and
wherein the upper portions of the second division pattern contact upper surfaces of the lower portions, respectively.
11. The vertical memory device of claim 1 , wherein the second division pattern includes lower portions spaced apart from one another in the second direction and connected to the third division patterns, and
wherein the upper portions of the second division pattern are spaced apart from one another on each of the lower portions, and each contact an upper surface of a corresponding one of the lower portions.
12. A vertical memory device comprising:
gate electrode structures each including gate electrodes spaced apart from one another on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, wherein each of the gate electrodes extends in a second direction substantially parallel to the upper surface of the substrate, and the gate electrode structures are spaced apart from one another in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction;
channels each extending through one of the gate electrode structures in the first direction;
a first division pattern extending in the second direction between first ones of the gate electrode structures neighboring in the third direction;
a second division pattern and a third division pattern alternately disposed in the second direction between second ones of the gate electrode structures neighboring in the third direction; and
a support layer on the gate electrode structures, wherein the support layer is at substantially the same height as upper portions of the first and second division patterns and contacting the upper portions of the first and second division patterns,
wherein the second division pattern includes lower portions spaced apart from one another in the second direction and connected to the third division patterns, and
wherein the upper portions of the second division pattern commonly contact upper surfaces of neighboring lower portions of the second division pattern in the second direction.
13. The vertical memory device of claim 12 , wherein the third division pattern overlaps the lower portion of the second division pattern in the first direction.
14. The vertical memory device of claim 12 , wherein a width in the third direction of the upper portion of the second division pattern is greater than that of the lower portions thereof.
15. The vertical memory device of claim 12 , wherein a distance of upper surfaces of the lower portions of the second division pattern from the substrate is greater than a distance of an upper surface of the third division pattern from the substrate.
16. A vertical memory device comprising:
gate electrode structures each including gate electrodes spaced apart from one another on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, wherein each of the gate electrodes extends in a second direction substantially parallel to the upper surface of the substrate, and the gate electrode structures are spaced apart from one another in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction;
channels each extending through one of the gate electrode structures in the first direction;
a first division pattern including:
a first lower portion extending in the second direction between first ones of the gate electrode structures neighboring in the third direction to separate the first ones of the gate electrode structures from one another; and
first upper portions spaced apart from one another in the second direction, and contacting an upper surface of the first lower portion;
a second division pattern including:
second lower portions spaced apart from one another in the second direction and disposed between second ones of the gate electrode structures; and
second upper portions contacting upper surfaces of the second lower portions;
third division patterns disposed between the second lower portions of the second division pattern; and
a support layer on the gate electrode structures, and facing sidewalls of the first and second upper portions of the first and second division patterns, respectively.
17. The vertical memory device of claim 16 , wherein the first and second upper portions of the first and second division patterns, respectively, are at substantially the same height.
18. The vertical memory device of claim 16 , wherein widths in the third direction of the first and second upper portions of the first and second division patterns, respectively, are greater than widths in the third direction of the first and second lower portions of the first and second division patterns, respectively.