Identifying and marking failed egress links in data plane
A method of identifying a failed egress path of a hardware forwarding element. The method detects an egress link failure in a data plane of the forwarding element. The method generates a link failure signal in the data plane identifying the failed egress link. The method generates a packet that includes the identification of the egress link based on the link failure signal. The method sets the status of the egress link to failed in the data plane based on the identification of the egress link in the generated packet.
1. A network switch integrated circuit for use in packet forwarding in a network, the network switch integrated circuit comprising:
ingress packet data processing pipeline hardware and egress packet data processing pipeline hardware for use in matching header field data of packet data associated with one or more packets received by the network switch integrated circuit to programmable match-action table data to determine one or more packet processing-related actions that correspond to the header field data, the one or more packet processing-related actions to be carried out in processing of the packet data;
shared buffer memory to be shared between the ingress packet data processing pipeline hardware and the egress packet data processing pipeline hardware for use in (1) storage of received packet data from the ingress packet data processing pipeline hardware and (2) provision of the received packet data to the egress packet data processing pipeline hardware;
wherein:
the ingress packet data processing pipeline hardware and the egress packet data processing pipeline hardware comprise respective pluralities of packet data processing pipelines;
when the network switch integrated circuit is in operation:
the programmable match-action table data is programmable based upon software-generated configuration data to be provided to the network switch integrated circuit;
the network switch integrated circuit is to implement the one or more packet processing-related actions;
the one or more packet processing-related actions are associated with equal-cost multi-path routing;
the one or more packet processing-related actions are programmable to comprise:
one or more operations to modify at least one packet header; and
one or more next hop determination operations;
the network switch integrated circuit is to generate flow-related information and statistics-related information usable in association with software-defined networking;
the flow-related information is related to data flow rate; and
the statistics-related information is related to packet count information, and byte count information.
2. The network switch integrated circuit of claim 1 , wherein:
the network switch integrated circuit comprises ternary content addressable memory to store the programmable match-action table data.
3. A non-transitory machine-readable storage medium storing instructions that are executable by a network switch integrated circuit, the network switch integrated circuit being for use in packet forwarding in a network, the network switch integrated circuit comprising ingress packet data processing pipeline hardware and egress packet data processing pipeline hardware, the network switch integrated circuit also comprising buffer memory that is to be shared between the ingress packet data processing pipeline hardware and the egress packet data processing pipeline hardware, the instructions, when executed by the network switch integrated circuit resulting in the network switch integrated circuit being configured to perform operations comprising:
matching, by the ingress packet data processing pipeline hardware and the egress packet data processing pipeline hardware, header field data of packet data associated with one or more packets received by the network switch integrated circuit to programmable match-action table data to determine one or more packet processing-related actions that correspond to the header field data, the one or more packet processing-related actions to be carried out in processing of the packet data;
storing, in the buffer memory, received packet data from the ingress packet data processing pipeline hardware; and
providing, from the buffer memory, the received packet data to the egress packet data processing pipeline hardware; and
wherein:
the ingress packet data processing pipeline hardware and the egress packet data processing pipeline hardware comprise respective pluralities of packet data processing pipelines;
when the network switch integrated circuit is in operation:
the programmable match-action table data is programmable based upon software-generated configuration data to be provided to the network switch integrated circuit;
the network switch integrated circuit is to implement the one or more packet processing-related actions;
the one or more packet processing-related actions are associated with equal-cost multi-path routing;
the one or more packet processing-related actions are programmable to comprise:
one or more operations to modify at least one packet header; and
one or more next hop determination operations;
the network switch integrated circuit is to generate flow-related information and statistics-related information usable in association with software-defined networking;
the flow-related information is related to data flow rate; and
the statistics-related information is related to packet count information, and byte count information.
4. The non-transitory machine-readable storage medium of claim 3 , wherein:
the network switch integrated circuit comprises ternary content addressable memory to store the programmable match-action table data.
5. A method implemented by a network switch integrated circuit, the network switch integrated circuit being for use in packet forwarding in a network, the network switch integrated circuit comprising ingress packet data processing pipeline hardware and egress packet data processing pipeline hardware, the network switch integrated circuit also comprising buffer memory that is to be shared between the ingress packet data processing pipeline hardware and the egress packet data processing pipeline hardware, the method comprising:
matching, by the ingress packet data processing pipeline hardware and the egress packet data processing pipeline hardware, header field data of packet data associated with one or more packets received by the network switch integrated circuit to programmable match-action table data to determine one or more packet processing-related actions that correspond to the header field data, the one or more packet processing-related actions to be carried out in processing of the packet data;
storing, in the buffer memory, received packet data from the ingress packet data processing pipeline hardware; and
providing, from the buffer memory, the received packet data to the egress packet data processing pipeline hardware; and
wherein:
the ingress packet data processing pipeline hardware and the egress packet data processing pipeline hardware comprise respective pluralities of packet data processing pipelines;
when the network switch integrated circuit is in operation:
the programmable match-action table data is programmable based upon software-generated configuration data to be provided to the network switch integrated circuit;
the network switch integrated circuit is to implement the one or more packet processing-related actions;
in a configuration, the one or more packet processing-related actions are associated with equal-cost multi-path routing;
the one or more packet processing-related actions are programmable to comprise:
one or more operations to modify at least one packet header; and
one or more next hop determination operations;
the network switch integrated circuit is to generate flow-related information and statistics-related information usable in association with software-defined networking;
the flow-related information is related to data flow rate; and
the statistics-related information is related to packet count information, and byte count information.
6. The method of claim 5 , wherein:
the network switch integrated circuit comprises ternary content addressable memory to store the programmable match-action table data.