Secure logic locking and configuration with camouflaged programmable micro netlists
The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.
1. A semiconductor chip comprising:
a plurality of interconnected logic cells for performing a core logic function of the chip;
at least a portion of non-volatile memory (NVM) for storing at least configuration data for the chip;
a programmable micro netlist (PMNL) circuit, including at least one programming input, wherein:
the PMNL circuit is constructed using at least one uncamouflaged logic gate and at least one camouflaged logic gate;
the programming input is operationally coupled to the configuration data stored in the NVM; and
wherein an operational function of the PMNL circuit contributes to the core logic function of the chip when the programming input is in a first logical state, and does not contribute to the core logic function when the programming input is in a second logical state.
2. The chip of claim 1 , wherein the camouflaged logic gate performs a first logical cell function and has a physical layout substantially indistinguishable from a physical layout of an uncamouflaged logic gate performing a second logical cell function.
3. The chip of claim 1 , wherein a physical layout of the camouflaged logic gate differs from a physical layout of the uncamouflaged logic gate by an eliminated structure.
4. The chip of claim 1 , wherein a physical layout of the camouflaged logic gate differs from a physical layout of the uncamouflaged logic gate by an additional structure.
5. The chip of claim 1 , wherein an input of the camouflaged logic gate is connected to at least one of another of the plurality of interconnected logic cells.
6. The chip of claim 1 , wherein the PMNL circuit comprises a storage element communicatively coupled between the NVM and the programming input to store the configuration data for the chip.
7. The chip of claim 6 , wherein the storage element is initialized at boot time from the NVM.
8. The chip of claim 7 , wherein the configuration data is secret and cannot be read or written without permission.
9. The chip of claim 1 , further comprising an address decoder, communicatively coupled between the NVM and a storage element, wherein the address decoder further comprises another camouflaged logic cell.
10. The chip of claim 1 , wherein at least a portion of the configuration data comprises programming data for programming the camouflaged logic gate.
11. A method of fabricating a semiconductor chip, comprising:
defining core logic having a plurality of interconnected logic cells that perform a core logic function of the chip;
defining a programmable micro netlist (PMNL) circuit, the PMNL circuit having a plurality of interconnected logic gates, the PMNL comprising:
an uncamouflaged logic gate, and a camouflaged logic gate;
a programming input communicatively coupleable to a non-volatile memory (NVM) to receive configuration data to configure the PMNL to perform an operational function of the PMNL that contributes to the core logic function of the chip when the programming input is in a first logical state, and does not contribute to the core logic function of the chip when the programming input is in a second logical state;
substituting the PMNL for a subset of the plurality of interconnected logic cells.
12. The method of claim 11 , wherein the camouflaged logic gate performs a first logical cell function and has a physical layout substantially indistinguishable from a physical layout of an uncamouflaged logic gate performing a second logical cell function.
13. The method of claim 11 , wherein a physical layout of the camouflaged logic gate differs from a physical layout of the uncamouflaged logic gate by an eliminated structure.
14. The method of claim 11 , wherein a physical layout of the camouflaged logic gate differs from a physical layout of the uncamouflaged logic gate by an additional structure.
15. The method of claim 11 , wherein an input of the camouflaged logic gate is connected to at least one of the plurality of interconnected logic cells.
16. The method of claim 11 , wherein the PMNL circuit comprises a storage element communicatively coupled between the NVM and the programming input to store the configuration data for the chip.
17. The method of claim 16 , wherein the storage element is initialized at boot time from the NVM.
18. The method of claim 17 , wherein the configuration data is secret and cannot be read or written without permission.
19. The method of claim 11 , further comprising an address decoder, communicatively coupled between the NVM and a storage element, wherein the address decoder further comprises another camouflaged logic cell.
20. A semiconductor chip manufactured by performing steps comprising the steps of:
defining core logic having a plurality of interconnected logic cells that perform a core logic function of the chip;
defining a programmable micro netlist (PMNL) circuit, the PMNL circuit having a plurality of interconnected logic gates, the PMNL comprising:
an uncamouflaged logic gate, and a camouflaged logic gate;
a programming input communicatively coupleable to a non-volatile memory (NVM) to receive configuration data to configure the PMNL to perform an operational function of the PMNL that contributes to the core logic function of the chip when the programming input is in a first logical state, and does not contribute to the core logic function of the chip when the programming input is in a second logical state;
substituting the PMNL for a subset of the plurality of interconnected logic cells, wherein the plurality of interconnected logic gates comprise:
an uncamouflaged logic gate for performing a first logic gate function and having a first physical layout; and
a camouflaged logic gate for performing a second logic gate function and having a second physical layout substantially indistinguishable from the first physical layout.