Resistive memory device and method of manufacturing the resistive memory device
A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.
1. A method of manufacturing a resistive memory device, the method comprising:
providing a semiconductor substrate having a plurality of memory cell arrays (MAT) regions and a plurality of row control regions between the MAT regions;
forming a local word line switch on the semiconductor substrate corresponding to the row control region; and
forming an insulating structure including a connection path having a spiral bypass structure on the local word line switch, the connection path having a structure connected with the local word line switch.
2. The method of claim 1 , wherein forming the insulating structure having the connection path comprises:
forming a first insulating interlayer on the semiconductor substrate with the local word line switch;
forming a first plug, which is connected with the local word line switch, in the first insulating interlayer;
forming a first wiring on the first insulating interlayer, the first wiring configured to make contact with the first plug;
forming a second insulating interlayer on the first wiring;
forming a second plug, which is connected with the first wiring, in the second insulating interlayer;
forming a second wiring on the second insulating interlayer;
forming a third insulating interlayer on the second wiring; and
forming a third plug, which is connected with the second wiring, in a portion of the third insulating interlayer corresponding to the first plug,
wherein the word line is formed on the third insulating interlayer to make contact with the third plug.
3. The method of claim 1 , wherein the first plug and the third plug are formed at first edge portions of the first and second wirings, and the second plug is formed at a second edge portion of the first and second wirings opposite to the first edge portions.
4. The method of claim 1 , further comprising:
is forming a phase changeable layer on the word line;
forming a conductive layer on the phase changeable layer; and
patterning the conductive layer and the phase changeable layer to form a bit line and a phase changeable memory cell intersected with the word line.
5. The method of claim 1 , wherein forming the insulating structure having the connection path comprises:
forming a first insulating interlayer on the semiconductor substrate with the local word line switch;
forming a first plug, which is connected with the local word line switch, in the first insulating interlayer;
forming a first wiring on the first insulating interlayer, the first wiring configured to make contact with the first plug;
forming a second insulating interlayer on the first wiring; and
forming a second plug, which is connected with the first wiring, in the second insulating interlayer,
wherein the word line is formed on the second insulating interlayer to make contact with the second plug.
6. The method of claim 1 , wherein the second plug is formed at a position corresponding to the first plug.