Artificial reality system having system-on-a-chip (SoC) integrated circuit components including stacked SRAM

1. An artificial reality system comprising: a head mounted display (HMD) configured to output artificial reality content, the HMD including at least one stacked integrated circuit component, wherein the at least one stacked integrated circuit component comprises: a system-on-a-chip (SoC) die having a frontside and a backside, wherein the frontside of the SoC die includes an active area including one or more active elements and one or more Input/Output (I/O) pads, and wherein the frontside of the SoC die further includes at least one non-active area outside of the active area; a static random-access memory (SRAM) subcomponent having a frontside and a backside, wherein the frontside of the SRAM subcomponent includes an active area including one or more active elements and one or more I/O pads bonded to the one or more I/O pads of the SoC die in a face-to-face, vertically stacked arrangement with no intermediate redistribution layer (RDL) routing; and a plurality of through-silicon vias (TSVs) formed from the backside of the SoC die to the frontside of the SoC die, wherein the plurality of TSVs are formed in the at least one non-active area of the SoC die and wherein none of the plurality of the TSVs are formed within the active area of the SoC die.

2. The artificial reality system of claim 1 wherein the at least one non-active area is located around the periphery of the active area.

3. The artificial reality system of claim 2 wherein the TSVs are formed in the at least one non-active area around the periphery of the active area.

4. The artificial reality system of claim 1 wherein the plurality of TSVs are formed from the backside of the SoC die to bonding pads patterned on or near the frontside of the SoC die in the at least one non-active area.

5. The artificial reality system of claim 1 further comprising a plurality of conductive bumps patterned on the backside of the SoC die.

6. The artificial reality system of claim 1 further comprising redistribution layers (RDLs) patterned on the backside of the SoC die.

7. The artificial reality system of claim 1 further comprising:

a plurality of sensors configured to output motion data representative of motion of a user;

wherein the SoC processes the motion data representative of motion of a user received from one or more of the plurality of sensors.

8. The artificial reality system of claim 7 wherein the plurality of sensors includes at least one inertial measurement unit.

9. The artificial reality system of claim 1 further comprising:

one or more image capture devices configured to output image data representative of a physical environment corresponding to a viewing perspective of the HMD;

wherein the SoC processes the image data representative of the physical environment received from one or more of the image capture devices.

10. The artificial reality system of claim 1 wherein the SRAM subcomponent includes a single SRAM die.

11. The artificial reality system of claim 1 wherein the SRAM subcomponent includes a stack of multiple SRAM die.

12. An integrated circuit component comprising: a system-on-a-chip (SoC) die having a frontside and a backside, wherein the frontside of the SoC die includes an active area including one or more active elements and one or more Input/Output (O/I) pads, and wherein the frontside of the SoC die further includes at least one non-active area outside of the active area; a static random-access memory (SRAM) subcomponent having a frontside and a backside, wherein the frontside of the SRAM subcomponent includes an active area including one or more active elements and one or more I/O pads bonded to the one or more I/O pads of the SoC die in a face-to-face, vertically stacked arrangement with no intermediate redistribution layer (RDL) routing; and a plurality of through-silicon vias (TSVs) formed from the backside of the SoC die to the frontside of the SoC die, wherein each of the plurality of TSVs are formed in the at least one non-active area of the SoC die and wherein none of the plurality of the TSVs are formed within the active area of the SoC die.

13. The integrated circuit component of claim 12 wherein the at least one non-active area is located around the periphery of the active area.

14. The integrated circuit component of claim 13 wherein the TSVs are formed in the at least one non-active area around the periphery of the active area.

15. The integrated circuit component of claim 12 wherein the plurality of TSVs are formed from the backside of the SoC die to bonding pads patterned on or near the frontside of the SoC die in the at least one non-active area.

16. The integrated circuit component of claim 12 further comprising a plurality of solder bumps patterned on the backside of the SoC die.

17. The integrated circuit component of claim 12 further comprising redistribution layers (RDLs) patterned on the backside of the SoC die.

18. The integrated circuit component of claim 12 wherein the SRAM subcomponent includes a single SRAM die.

19. The integrated circuit component of claim 12 wherein the SRAM subcomponent includes a stack of multiple SRAM die.

20. A method comprising: providing a system-on-a-chip (SoC) die having a frontside and an oppositely facing backside; bonding one or more Input/Output (I/O) pads on the frontside of the SoC die to one or more I/O pads on a frontside of a static random-access memory (SRAM) subcomponent in a face-to-face, vertically stacked arrangement with no intermediate redistribution layer (RDL) routing, wherein the frontside of the SoC die includes an active area including one or more active elements, and wherein the frontside of the SoC die further includes at least one non-active area outside of the active area, and wherein the frontside of the SRAM subcomponent includes an active area including one or more active elements; thinning the SoC die from a first thickness to a second thickness, wherein the first thickness is relatively greater than the second thickness, and wherein the thinning includes thinning the SoC die from the backside of the SoC die; forming a plurality of through-silicon vias (TSVs) from the backside of the SoC die to the frontside of the SoC die, wherein the plurality of TSVs are formed in the at least one non-active area of the SoC die and wherein none of the plurality of the TSVs are formed within the active area of the SoC die; and metallizing the TSVs from the backside of the SoC die to the frontside of the SoC die.

21. The method of claim 20 wherein thinning the SoC die includes performing a mechanical grinding process on the backside of the SoC die.

22. The method of claim 20 wherein the TSVs are formed by a via-last through-silicon via technology.

23. The method of claim 20 further comprising patterning of redistribution layers (RDLs) on the backside of the SoC die.

24. The method of claim 20 , wherein bonding the active side of the SoC die to the active side of the SRAM subcomponent in the face-to-face, vertically stacked arrangement is performed at a first fabricating facility, and wherein thinning the SoC die from the first thickness to the second thickness, forming the plurality of through-silicon vias from the backside of the SoC die to the front side of the SoC die, and metallizing the TSVs from the backside of the SoC die are performed at a second, different fabricating facility.

25. The method of claim 20 wherein thinning the SoC die includes thinning the backside of the SoC die from a thickness of about 775 micrometers (μm) to a thickness in a range of about 25 to 200 μm.

26. The method of claim 20 wherein thinning the SoC die includes thinning the backside of the SoC die to the second thickness such that TSVs may be formed from the backside of the SoC die to bonding pads on the frontside of the SoC die without requiring a TSV reveal process.

27. The method of claim 20 wherein the at least one non-active area is located around the periphery of the active area.

28. The method of claim 20 further comprising patterning a plurality of conductive bumps on the backside of the SoC die.

29. The method of claim 20 wherein metallizing the TSVs further comprises metallizing the TSVs from the backside of the SoC die to bonding pads patterned on the frontside of the SoC die in the at least one non-active area.

30. The method of claim 20 wherein the SRAM subcomponent includes a single SRAM die.

31. The method of claim 20 wherein the SRAM subcomponent includes a stack of multiple SRAM die.

32. The method of claim 20 wherein thinning the SoC die from a first thickness to a second thickness and forming the plurality of through-silicon vias (TSVs) from the backside of the SoC die to the frontside of the SoC die occur before bonding the frontside of the SoC die to a frontside of the static random-access memory (SRAM) subcomponent in a face-to-face, vertically stacked arrangement.