Power loss protection in memory sub-systems
Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.
1. A system comprising:
a plurality of memory components comprising non-volatile memory components and a volatile cache; and
a processing device, operatively coupled with the plurality of memory components, to perform operations comprising:
receiving a write command to write data to the volatile cache of the plurality of memory components;
detecting a trigger event at a device associated with the plurality of memory components;
identifying a portion of the non-volatile memory components based on the trigger event; and
allocating the data to the portion of the identified portion of the non-volatile memory components.
2. The system of claim 1 , wherein the identifying the portion of the non-volatile memory components comprises:
determining a ranking of the portion of the non-volatile memory components; and
identifying the portion of the non-volatile memory components based on the ranking.
3. The system of claim 2 , wherein the determining the ranking of the portion of the non-volatile memory components comprises:
performing a performance test upon the non-volatile memory components; and
determining the ranking of the portion of the non-volatile memory components among the non-volatile memory components based on a result of the performance test.
4. The system of claim 2 , wherein the non-volatile memory components comprise a set of flash blocks, and the identifying the portion of the non-volatile memory components comprises:
determining a write time of each flash block among the set of flash blocks of the non-volatile memory components;
ranking the set of flash blocks based on the write time of each flash block among the set of flash blocks; and
identifying the portion of the non-volatile memory components based on the ranking of the set of flash blocks.
5. The system of claim 1 , wherein the non-volatile memory components comprise NAND flash memory that comprises single-level cell NAND flash memory.
6. The system of claim 1 , wherein the trigger event comprises asynchronous power loss to the system.
7. The system of claim 1 , wherein the portion of the non-volatile memory components is a first portion, and the operations further comprise:
performing a performance test upon the non-volatile memory components at a predetermined interval;
determining a first performance metric of the first portion of the non-volatile memory components transgresses a minimum threshold value;
identifying a second portion of the non-volatile memory components based on a second performance metric of the second portion of the non-volatile memory components; and
allocating the data to the second portion of the non-volatile memory components.
8. A method comprising:
receiving a write command to write data to a volatile cache of a plurality of memory components;
detecting a trigger event at a device associated with the plurality of memory components;
identifying a portion of the non-volatile memory components based on the trigger event; and
allocating the data to the portion of the identified portion of the non-volatile memory components.
9. The method of claim 8 , wherein the identifying the portion of the non-volatile memory components comprises:
determining a ranking of the portion of the non-volatile memory components; and
identifying the portion of the non-volatile memory components based on the ranking.
10. The method of claim 9 , wherein the determining the ranking of the portion of the non-volatile memory components comprises:
performing a performance test upon the non-volatile memory components; and
determining the ranking of the portion of the non-volatile memory components among the non-volatile memory components based on a result of the performance test.
11. The method of claim 9 , wherein the non-volatile memory components comprise a set of flash blocks, and the identifying the portion of the non-volatile memory components comprises:
determining a write time of each flash block among the set of flash blocks of the non-volatile memory components;
ranking the set of flash blocks based on the write time of each flash block among the set of flash blocks; and
identifying the portion of the non-volatile memory components based on the ranking of the set of flash blocks.
12. The method of claim 8 , wherein the non-volatile memory components comprise NAND flash memory that comprises single-level cell NAND flash memory.
13. The method of claim 8 , wherein the trigger event comprises asynchronous power loss to the system.
14. The method of claim 8 , wherein the portion of the non-volatile memory components is a first portion, and the operations further comprise:
performing a performance test upon the non-volatile memory components at a predetermined interval;
determining a first performance metric of the first portion of the non-volatile memory components transgresses a minimum threshold value;
identifying a second portion of the non-volatile memory components based on a second performance metric of the second portion of the non-volatile memory components; and
allocating the data to the second portion of the non-volatile memory components.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive a write command to write data to a volatile cache of a plurality of memory components;
detect a trigger event at a device associated with the plurality of memory components;
identifying a portion of the non-volatile memory components based on the trigger event; and
allocate the data to the portion of the identified portion of the non-volatile memory components.
16. The non-transitory machine-readable storage medium of claim 15 , wherein the identifying the portion of the non-volatile memory components comprises:
determining a ranking of the portion of the non-volatile memory components; and
identifying the portion of the non-volatile memory components based on the ranking.
17. The non-transitory machine-readable storage medium of claim 16 , wherein the determining the ranking of the portion of the non-volatile memory components comprises:
performing a performance test upon the non-volatile memory components; and
determining the ranking of the portion of the non-volatile memory components among the non-volatile memory components based on a result of the performance test.
18. The non-transitory machine-readable storage medium of claim 16 , wherein the non-volatile memory components comprise a set of flash blocks, and the identifying the portion of the non-volatile memory components comprises:
determining a write time of each flash block among the set of flash blocks of the non-volatile memory components;
ranking the set of flash blocks based on the write time of each flash block among the set of flash blocks; and
identifying the portion of the non-volatile memory components based on the ranking of the set of flash blocks.
19. The non-transitory machine-readable storage medium of claim 15 , wherein the non-volatile memory components comprise NAND flash memory that comprises single-level cell NAND flash memory.
20. The non-transitory machine-readable storage medium of claim 15 , wherein the trigger event comprises asynchronous power loss to the system.