In-memory computing with cache coherent protocol
A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.
1. A system for computing, the system comprising:
a memory, the memory comprising one or more function-in-memory circuits; and
a cache coherent protocol interface circuit having a first interface and a second interface,
a function-in-memory circuit of the one or more function-in-memory circuits being configured to perform an operation on operands including a first operand retrieved from the memory, to form a result,
the first interface of the cache coherent protocol interface circuit being connected to the memory, and
the second interface of the cache coherent protocol interface circuit being configured as a cache coherent protocol interface on a bus interface.
2. The system of claim 1 , wherein:
the function-in-memory circuits are arranged in a single instruction, multiple data configuration; or
the function-in-memory circuits are arranged in a systolic configuration.
3. The system of claim 1 , wherein:
the cache coherent protocol interface circuit is a Compute Express Link (CXL) interface circuit, and
the bus interface is a Peripheral Component Interconnect express (PCIe) endpoint interface.
4. The system of claim 1 , wherein a function-in-memory circuit of the one or more function-in-memory circuits is on a semiconductor chip with a dynamic random-access memory.
5. The system of claim 1 , wherein the first interface is configured to operate according to a protocol selected from the group consisting of DDR2, DDR3, DDR4, and DDR5.
6. The system of claim 1 , wherein a function-in-memory circuit of the one or more function-in-memory circuits comprises:
a plurality of registers,
a plurality of multiplexers, and
an arithmetic logic unit.
7. The system of claim 1 , wherein a function-in-memory circuit of the one or more function-in-memory circuits is configured to perform an arithmetic operation selected from the group consisting of addition, subtraction, multiplication, and division.
8. The system of claim 1 , wherein a function-in-memory circuit of the one or more function-in-memory circuits is configured to perform an arithmetic operation selected from the group consisting of floating-point addition, floating-point subtraction, floating-point multiplication, and floating-point division.
9. The system of claim 1 , wherein a function-in-memory circuit of the one or more function-in-memory circuits is configured to perform a logical operation selected from the group consisting of bitwise AND, bitwise OR, bitwise exclusive OR, and bitwise ones complement.
10. The system of claim 1 , wherein a function-in-memory circuit of the one or more function-in-memory circuits is configured, in a first state, to store the result in the memory, and, in a second state, to send the result to the cache coherent protocol interface circuit.
11. The system of claim 1 , further comprising a host processing circuit connected to the second interface.
12. The system of claim 11 , wherein the host processing circuit comprises a PCIe root complex having a root port connected to the second interface.
13. A system for computing, the system comprising:
a memory; and
a cache coherent protocol interface circuit having a first interface and a second interface,
the cache coherent protocol interface circuit being configured to perform an arithmetic operation on data stored in the memory,
the first interface of the cache coherent protocol interface circuit being connected to the memory, and
the second interface being configured as a cache coherent protocol interface on a bus interface.
14. The system of claim 13 , wherein:
the memory comprises one or more function-in-memory circuits, and
a function-in-memory circuit of the one or more function-in-memory circuits is configured to perform an operation on operands including a first operand retrieved from the memory, to form a result.
15. The system of claim 14 , wherein:
the function-in-memory circuits are arranged in a single instruction, multiple data configuration; or
the function-in-memory circuits are arranged in a systolic configuration.
16. The system of claim 14 , wherein:
the cache coherent protocol interface circuit is a Compute Express Link (CXL) interface circuit, and
the bus interface is a Peripheral Component Interconnect express (PCIe) endpoint interface.
17. The system of claim 14 , wherein a function-in-memory circuit of the one or more function-in-memory circuits is on a semiconductor chip with a dynamic random-access memory.
18. The system of claim 14 , wherein the first interface is configured to operate according to a protocol selected from the group consisting of DDR2, DDR3, DDR4, DDR5, GDDR, HBM, and LPDDR.
19. The system of claim 14 , wherein a function-in-memory circuit of the one or more function-in-memory circuits is configured, in a first state, to store the result in the memory, and, in a second state, to send the result to the cache coherent protocol interface circuit.
20. A method for computing, the method comprising:
sending, by a host processing circuit, to a CXL interface circuit, one or more CXL packets;
sending, by the CXL interface circuit, in response to receiving the CXL packets, to a function-in-memory circuit in a memory connected to the CXL interface circuit, an instruction; and
performing, by the function-in-memory circuit, an operation, in accordance with the instruction, on operands including a first operand retrieved from the memory, to form a result.