Shared memory workloads using existing network fabrics
Shared memory workloads using existing network fabrics, including: presenting, by a Memory Mapped Input/Output (MMIO) translator, memory of the MMIO translator as a portion of a memory space of a host; receiving, by the MMIO translator, a first interrupt from an input/output (I/O) adapter; and storing, by the MMIO translator, without sending the first interrupt to an operating system, data associated with the first interrupt from the I/O adapter into the memory of the MMIO translator.
1. A method of shared memory workloads, the method comprising:
presenting, by a Memory Mapped Input/Output (MMIO) translator, memory of the MMIO translator as a portion of a memory space of a host, wherein the memory of the MMIO translator comprises an MMIO address range;
receiving, by the MMIO translator, a first interrupt from an input/output (I/O) adapter; and
storing, by the MMIO translator, without sending the first interrupt to an operating system, data associated with the first interrupt from the I/O adapter into the MMIO address range in the memory of the MMIO translator.
2. The method of claim 1 , wherein storing the data associated with the first interrupt from the I/O adapter comprises storing the data associated with the first interrupt as a portion of a corpus of data from the I/O adapter, wherein the first interrupt was sent by the I/O adapter for the operating system, and wherein receiving, by the MMIO translator, the first interrupt from the I/O adapter comprising intercepting, by the MMIO translator, the first interrupt.
3. The method of claim 2 , further comprising sending a second interrupt to the operating system to access the corpus of data.
4. The method of claim 3 , further comprising determining, based on one or more of the first interrupt or a state of the corpus of data, to send the second interrupt.
5. The method of claim 1 , wherein the memory space of the host comprises one or more memory modules in a same coherency space as the memory of the MMIO translator.
6. The method of claim 1 , wherein the data associated with the first interrupt is stored into the memory of the MMIO translator using Direct Memory Access.
7. The method of claim 1 , wherein the I/O adapter comprises one or more of a network adapter or a Peripheral Component Interconnect express (PCIe) adapter.
8. An apparatus for shared memory workloads configured to perform steps comprising:
presenting, by a Memory Mapped Input/Output (MMIO) translator, memory of the MMIO translator as a portion of a memory space of a host, wherein the memory of the MMIO translator comprises an MMIO address range;
receiving, by the MMIO translator, a first interrupt from an input/output (I/O) adapter; and
storing, by the MMIO translator, without sending the first interrupt to an operating system, data associated with the first interrupt from the I/O adapter into the MMIO address range in the memory of the MMIO translator.
9. The apparatus of claim 8 , wherein storing the data associated with the first interrupt from the I/O adapter comprises storing the data associated with the first interrupt as a portion of a corpus of data from the I/O adapter.
10. The apparatus of claim 9 , wherein the steps further comprise sending a second interrupt to the operating system to access the corpus of data.
11. The apparatus of claim 10 , wherein the steps further comprise determining, based on one or more of the first interrupt or a state of the corpus of data, to send the second interrupt.
12. The apparatus of claim 8 , wherein the memory space of the host comprises one or more memory modules in a same coherency space as the memory of the MMIO translator.
13. The apparatus of claim 8 , wherein the data associated with the first interrupt is stored into the memory of the MMIO translator using Direct Memory Access.
14. The apparatus of claim 8 , wherein the I/O adapter comprises one or more of a network adapter or a Peripheral Component Interconnect express (PCIe) adapter.
15. A system for shared memory workloads comprising:
a processor;
an Input/Output (I/O) Adapter; and
a Memory Mapped Input/Output (MMIO) translator configured to perform steps comprising:
presenting, by the MMIO translator, memory of the MMIO translator as a portion of a memory space of a host, wherein the memory of the MMIO translator comprises an MMIO address range;
receiving, by the MMIO translator, a first interrupt from the I/O adapter; and
storing, by the MMIO translator, without sending the first interrupt to an operating system, data associated with the first interrupt from the I/O adapter into the MMIO address range in the memory of the MMIO translator.
16. The system of claim 15 , wherein storing the data associated with the first interrupt from the I/O adapter comprises storing the data associated with the first interrupt as a portion of a corpus of data from the I/O adapter.
17. The system of claim 16 , wherein the steps further comprise sending a second interrupt to the operating system to access the corpus of data.
18. The system of claim 17 , wherein the steps further comprise determining, based on one or more of the first interrupt or a state of the corpus of data, to send the second interrupt.
19. The system of claim 15 , wherein the memory space of the host comprises one or more memory modules in a same coherency space as the memory of the MMIO translator.
20. The system of claim 15 , wherein the data associated with the first interrupt is stored into the memory of the MMIO translator using Direct Memory Access.