Low power biquad systems and methods
Biquad stage systems and methods include receiving at biquad sections a signal sample, generating, by each biquad section, a pair of output values based on the signal sample, including a first value based on fixed-point processing path and a second value emulating a floating-point processing path, and accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal. The biquad stage receives an N-bit input signal, which is processed by a biquad section. Delay elements delay the signal sample before input to other biquad sections. The delayed signal sample is input to the first processing path and the second processing path of a corresponding biquad stage. By performing the processing based on two paths, a more accurate result can be found when using a reduced word length in the multiply operations resulting in a lowering of the power consumption.
1. An infinite impulse response filter comprising:
a plurality of biquad sections, each biquad section configured to receive a signal sample and generate a pair of output values including:
a first path configured to process the signal sample based on fixed-point processing; and
a second path configured to process the signal sample based on changing a coefficient value by performing a first shift it in one direction and after forming a product, shift the product in the opposite direction so as to correct for the first shift;
a first plurality of delay elements configured to delay the signal sample, wherein:
the signal sample to a first biquad section of the plurality of biquad sections is not delayed;
the signal sample to a second biquad section of the plurality of biquad sections is delayed using a first delay element of the first plurality of delay elements; and
the signal sample to a third biquad section of the plurality of biquad sections is delayed using a second delay element of the first plurality of delay elements;
an accumulator configured to receive and sum the pair of output values from each of the plurality of biquad sections to generate an accumulated signal;
a plurality of feedback biquad sections, each feedback biquad section configured to receive an accumulated signal output by the accumulator and generate a pair of feedback output values including:
a first feedback path configured to process the accumulated signal based on fixed-point processing; and
a second feedback path configured to process the accumulated signal based on changing a coefficient value by shifting it in one direction and after forming a product, shift the product in the opposite direction, wherein
an output of each feedback path of each of the plurality of feedback biquad sections are input to the accumulator; and
a second plurality of delay elements configured to delay the accumulated signal, wherein:
the accumulated signal to a first feedback biquad section of the plurality of feedback biquad sections is delayed using a first delay element of the second plurality of delay elements; and
the accumulated signal to a second feedback biquad section of the plurality of feedback biquad sections is delayed using a second delay element of the second plurality of delay elements.
2. The infinite impulse response filter of claim 1 , further configured to receive a sequence of N-bit input signal samples, which are processed by at least one of the plurality of biquad sections.
3. The infinite impulse response filter of claim 1 , wherein each biquad section includes a corresponding filter coefficient.
4. The infinite impulse response filter of claim 1 , wherein the first path is configured to multiply and shift the received signal sample.
5. The infinite impulse response filter of claim 1 , wherein the first path comprises a multiplier component and a plurality of multiplexers configured to perform bit shifting operations.
6. The infinite impulse response filter of claim 1 , wherein the second path comprises a plurality of multiplexers configured to perform operations in accordance with a plurality of coefficients.
7. The infinite impulse response filter of claim 6 , wherein the coefficients are configurable to implement low pass, high pass and all pass filters.
8. The infinite impulse response filter of claim 1 , wherein the accumulator comprises a first adder configured to sum the output values from the first path and a second adder configured to sum the output values from the second path.
9. The infinite impulse response filter of claim 8 , wherein the accumulator further comprises a register configured to store and output the accumulated value, which is fed back into the first adder.
10. A method comprising:
receiving at a plurality of biquad sections a signal sample, wherein each biquad section of the plurality of biquad sections comprises:
a first path configured to process the signal sample based on fixed-point processing; and
a second path configured to process the signal sample based on changing a coefficient value by performing a first shift in one direction and after forming a product, shift the product in the opposite direction so as to correct for the first shift
delaying, by a first plurality of delay elements, the signal sample prior to a second biquad section and a third biquad section of the plurality of biquad sections, wherein:
the signal sample to a first biquad section of the plurality of biquad sections is not delayed;
the signal sample to the second biquad section is delayed using a first delay element of the first plurality of delay elements; and
the signal sample to the third biquad section is delayed using a second delay element of the first plurality of delay elements; and
generating, by each biquad section, a pair of output values based on the signal sample using the first path and the second path; and
accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal.
11. The method of claim 10 , further comprising receiving an N-bit input signal, which is processed by at least one of the plurality of biquad sections.
12. The method of claim 10 , further comprising configuring each biquad section using a corresponding filter coefficient.
13. The method of claim 10 , wherein the plurality of biquad sections include forward paths receiving an input signal, and feedback paths receiving a processed output signal from an accumulator and/or a delayed processed output signal from the accumulator.
14. The method of claim 10 , wherein the fixed-point processing is configured to multiply the signal sample by a constant using one or more multiplexers.
15. The method of claim 10 , wherein a correction path comprises a coefficient that has been changed by shifting, an integer multiplier and a bit shifting of the product consisting of a plurality of multiplexers to compensate for the earlier change of the coefficient.
16. The method of claim 10 , wherein a correction path comprises a plurality of multiplexers configured to perform operations in accordance with a plurality of coefficients, and wherein the coefficients are configurable for low pass, high pass and all pass filter implementations.
17. The method of claim 10 , wherein an accumulator comprises a first adder configured to sum the output values from the first path and a second adder configured to sum the output values from the second path; and wherein the accumulator further comprises a register configured to store and output the accumulated value, which is fed back into the first adder.