System and method for tracking memory corrected errors by frequency of occurrence while reducing dynamic memory allocation
View Patent ↗An information handling system includes a processor and a basic input/output system (BIOS). The processor executes an operating system, and detects a corrected error from a memory controller of the information handling system. In response, the processor generates a system management interrupt (SMI). In response to the SMI the BIOS executes a SMI handler. The SMI handler detects a row of the corrected error within a dual inline memory module (DIMM) of the information handling system, and determines whether an entry for the row is located within a hash table. In response to the entry for the row being located within the hash table, the SMI handler increments an error count in a field of the entry for the row. Otherwise, the SMI handler adds a new entry for the row to the hash table, and increments an error count in a field of the new entry for the row.
1. An information handling system comprising:
a processor to execute an operating system of the information handling system, to detect a corrected error from a memory controller of the information handling system, and to generate a system management interrupt (SMI); and
a basic input/output system (BIOS) to receive the SMI from the processor, and in response to receiving the SMI, to execute an SMI handler, the SMI handler to:
detect a row of the corrected error within a dual inline memory module (DIMM) of the information handling system;
determine whether an entry for the row is located within a hash table;
in response to the entry for the row being located within the hash table, increment an error count in a field of the entry for the row; and
in response to the entry for the row not being located within the hash table:
add a new entry for the row to the hash table; and
increment an error count in a field of the new entry for the row.
2. The information handling system of claim 1 , wherein the SMI handler further to:
determine whether an error threshold has been exceeded for the DIMM; and
if the error threshold for the DIMM has been exceeded:
determine a row of the DIMM with a highest error count; and
perform a fault avoidance operation on the row with the highest error count.
3. The information handling system of claim 2 , wherein prior to the determination of whether the error threshold has been exceeded for the DIMM, the SMI handler further to:
determine whether a modulo of the error count equals zero; and
in response to the modulo of the error count equaling zero, perform the determining of whether the error threshold has been exceeded for the DIMM.
4. The information handling system of claim 2 , wherein prior to the determination of whether the error threshold has been exceeded for the DIMM, the SMI handler further to:
determine whether a modulo of the error count equals zero;
in response to the modulo of the error count equaling zero, sort entries in the hash table with from a highest error count to a lowest error count; and
in response to the sorting of the entries in the hash table, perform the determining of whether the error threshold has been exceeded for the DIMM.
5. The information handling system of claim 2 , the SMI handler further to:
clear the hash table; and
deallocate all dynamically allocated memory associated with the SMI handler.
6. The information handling system of claim 1 , wherein prior to the determination of whether the entry for the row is located within the hash table, the SMI handler further to:
determine whether a time limit for a leaky bucket counter for the DIMM has expired;
in response to the time limit expiring, clear an error count of the leaky bucket counter and incrementing the error count of the leaky bucket counter; and
in response to the time limit not expiring, increment the error count of the leaky bucket counter.
7. The information handling system of claim 6 , wherein the determination of whether the error threshold has been exceeded for the DIMM further comprises the SMI handler to compare the error count of the leaky bucket counter to the error threshold.
8. The information handling system of claim 2 , wherein the fault avoidance operation is a reliability availability and serviceability (RAS) corrective action selected based on a chipset associated with the processor.
9. The information handling system of claim 2 , wherein the RAS corrective action is selected from a group including: a double data rate (DDR) memory post-package repair operation on the row and an adaptive double device data correction operation on the row.
10. The information handling system of claim 1 , in response to the entry for the row being located within the hash table, the SMI handler further to copy a most recent error record data for the row into the new entry for the row.
11. A method comprising:
executing, by a processor of an information handling system, an operating system;
detecting a corrected error from a memory controller of the information handling system;
generating a system management interrupt (SMI);
detecting, by an SMI handler of a basic input/output system, a row of the corrected error within a dual inline memory module (DIMM) of the information handling system;
determining, by the SMI handler, whether an entry for the row is located within a hash table;
in response to the entry for the row being located within the hash table, incrementing an error count in a field of the entry for the row; and
in response to the entry for the row not being located within the hash table:
adding a new entry for the row to the hash table; and
incrementing an error count in a field of the new entry for the row.
12. The method of claim 11 , further comprising:
determining, by the SMI handler, whether an error threshold has been exceeded for the DIMM; and
if the error threshold for the DIMM has been exceeded:
determining, by the SMI handler, a row of the DIMM with a highest error count; and
performing, by the SMI handler, a fault avoidance operation on the row with the highest error count.
13. The method of claim 12 , wherein prior to the determining of whether the error threshold has been exceeded for the DIMM, the method further comprising:
determining, by the SMI handler, whether a modulo of the error count equals zero; and
in response to the modulo of the error count equaling zero, performing the determining of whether the error threshold has been exceeded for the DIMM.
14. The method of claim 12 , wherein prior to the determining of whether the error threshold has been exceeded for the DIMM, the method further comprising:
determining, by the SMI handler, whether a modulo of the error count equals zero;
in response to the modulo of the error count equaling zero, sorting, by the SMI handler, entries in the hash table with from a highest error count to a lowest error count; and
in response to the sorting of the entries in the hash table, performing the determining of whether the error threshold has been exceeded for the DIMM.
15. The method of claim 12 , further comprising:
clearing, by the SMI handler, the hash table; and
deallocating all dynamically allocated memory associated with the SMI handler.
16. The method of claim 12 , wherein prior to the determining of whether the entry for the row is located within the hash table, the method further comprising:
determining, by the SMI handler, whether a time limit for a leaky bucket counter for the DIMM has expired;
in response to the time limit expiring, clearing, by the SMI handler, an error count of the leaky bucket counter and incrementing the error count of the leaky bucket counter; and
in response to the time limit not expiring, incrementing, by the SMI handler, the error count of the leaky bucket counter.
17. The method of claim 16 , wherein the determining of whether the error threshold has been exceeded for the DIMM further comprises:
comparing, by the SMI handler, the error count of the leaky bucket counter to the error threshold.
18. The method of claim 11 , wherein in response to the entry for the row not being located within the hash table, the method further comprising:
copying, by the SMI handler, a most recent error record data for the row into the new entry for the row.
19. A non-transitory computer-readable medium including code that when executed by a processor causes the processor to perform a method, the method comprising:
executing an operating system;
detecting a corrected error from a memory controller of the information handling system;
generating a system management interrupt (SMI);
detecting, by an SMI handler of a basic input/output system, a row of the corrected error within a dual inline memory module (DIMM) of the information handling system;
determining whether an entry for the row is located within a hash table;
in response to the entry for the row being located within the hash table, incrementing an error count in a field of the entry for the row; and
in response to the entry for the row not being located within the hash table:
adding a new entry for the row to the hash table; and
incrementing an error count in a field of the new entry for the row.
20. The non-transitory computer-readable medium of claim 19 , wherein the method further comprises:
determining, by the SMI handler, whether an error threshold has been exceeded for the DIMM; and
if the error threshold for the DIMM has been exceeded:
determining, by the SMI handler, a row of the DIMM with a highest error count; and
performing, by the SMI handler, a fault avoidance operation on the row with the highest error count.