IP Library Granted Patent US 12,660,550
Granted Patent B2
US 12,660,550 · App. 16/918,889 · Granted Jun 16, 2026

Multi-zone silicon nitride wafer heater assembly having corrosion protective layer, and methods of making and using the same

Inventors: Ramesh Divakar (Arvada, CA); Matthew Simpson (Evergreen, CO); Alan Filer (Longmont, CO)
Assignee: CoorsTek, Inc.
H10P72/0432C04B35/584C04B35/6303C04B35/634C04B41/009C04B41/4539C04B41/5024C04B41/87F27D5/0037H05B3/12H05B3/283C04B2235/3224C04B2235/3418C04B2235/3873C04B2235/3891C04B2235/6025C04B2235/656C04B2235/658C04B2235/661H05B2203/037
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Quick Facts
Patent No.
US 12,660,550
App. No.
16/918,889
Granted
Jun 16, 2026
Kind
B2
Abstract

A wafer heater assembly comprises a heater substrate and a non-porous outermost layer. The heater substrate comprises silicon nitride (Si 3 N 4 ) and includes at least one heating element embedded therein. The non-porous outermost layer is associated with at least a first surface of the heater substrate. The non-porous outermost layer comprises a rare-earth (RE) disilicate (RE 2 Si 2 O 7 ); where RE is one of Yb and Y. The non-porous outermost layer includes an exposed surface configured to contact a wafer for heating, the exposed surface opposite the first surface of the heater substrate. Methods of making wafer heater assemblies are also disclosed as well as methods of using the wafer heater assembly.

Claims (29)

1 . A wafer heater assembly, the assembly comprising:

a heater substrate comprising nitride including at least one heating element embedded therein, the heater substrate having a first surface; and

a non-porous outermost layer proximal the first surface of the heater substrate, the non-porous outermost layer comprising a rare earth disilicate, wherein the rare earth disilicate comprises ytterbium disilicate (Yb 2 Si 2 O 7 );

wherein the non-porous outermost layer comprises an exposed surface and a second surface, wherein the exposed surface is configured to contact a wafer for heating, and wherein the second surface faces the first surface of the heater substrate; and

wherein the non-porous outermost layer realizes a Keiviite 001 peak intensity and a Keiviite 020 peak intensity, wherein the Keiviite 001 peak intensity is less than 95% of the Keiviite 020 intensity when tested using a theta-theta x-ray diffractometer, copper tube operated at 40 kV; and

wherein the wafer heater assembly is configured for use in fabricating semiconductor chips and for in-situ cleaning with halogen gases.

2 . The wafer heater assembly of claim 1 , wherein the non-porous outermost layer and the heater substrate further include an interface therebetween, and wherein the interface comprises between about 0 volume percent and at most about 5 volume percent porosity.

3 . The wafer heater assembly of claim 2 , wherein the interface comprises between about 0 volume percent and at most 1 volume percent porosity.

4 . The wafer heater assembly of claim 1 , wherein at least a portion of the rare earth disilicate comprises a Keiviite crystal structure and wherein the non-porous outermost layer comprises between about 50 volume percent and about 100 volume percent of the rare earth disilicate having the Keiviite crystal structure.

5 . The wafer heater assembly of claim 4 , wherein the non-porous outermost layer comprises between about 95 volume percent and about 100 volume percent of the rare earth disilicate having the Keiviite crystal structure.

6 . The wafer heater assembly of claim 1 , further comprising a supporting disk configured to support the heater substrate.

7 . The wafer heater assembly of claim 1 , wherein the at least one heating element embedded in the heater substrate includes a first heating element and a second heating element, the first heating element associated with a first heating zone and the second heating element associated with a second heating zone, and wherein a material of the at least one heating element is selected from the group consisting of molybdenum, niobium, rhenium, tantalum, tungsten, and alloys thereof, and wherein a distance between the first heating element and the second heating element is between about 0.05 cm and about 1 cm.

8 . The wafer heater assembly of claim 1 , wherein the non-porous outermost layer is adjacent the first surface of the heater substrate.

9 . The wafer heater assembly of claim 1 , wherein the assembly comprises an interposing layer, and wherein the interposing layer is disposed between the non-porous outermost layer and the heater substrate.

10 . The wafer heater assembly of claim 1 , wherein the nitride of the heater substrate is selected from the group consisting of silicon nitride, aluminum nitride, and combinations thereof.

11 . The wafer heater assembly of claim 1 , wherein the nitride of the heater substrate comprises silicon nitride.

12 . The wafer heater assembly of claim 11 , wherein the heater substrate comprises at least 10 volume percent beta silicon nitride (ß-Si 3 N 4 ).

13 . The wafer heater assembly of claim 12 , wherein an x-ray diffraction spectrum of the heater substrate comprises a beta silicon nitride ß-Si 3 N 4 101 peak intensity which is less than about 95% of a beta silicon nitride ß-Si 3 N 4 200 reflection-peak intensity when tested using a theta-theta x-ray diffractometer, copper tube operated at 40 kV.

14 . The wafer heater assembly of claim 12 , wherein the heater substrate comprises at least 50 volume percent beta silicon nitride (ß-Si 3 N 4 ).

15 . The wafer heater assembly of claim 12 , wherein the heater substrate comprises at least 90 volume percent beta silicon nitride (ß-Si 3 N 4 ).

16 . A wafer heater assembly, the assembly comprising:

a heater substrate comprising silicon nitride (Si 3 N 4 ), the heater substrate including at least one heating element embedded therein, the heater substrate having a first surface; and

a non-porous outermost layer proximal the first surface of the heater substrate, the non-porous outermost layer consisting essentially of ytterbium disilicate (Yb 2 Si 2 O 7 );

wherein the non-porous outermost layer realizes a Keiviite 001 peak intensity and a Keiviite 020 peak intensity, wherein the Keiviite 001 peak intensity is less than 95% of the Keiviite 020 intensity when tested using a theta-theta x-ray diffractometer, copper tube operated at 40 kV:

wherein the non-porous outermost layer comprises an exposed surface and a second surface, wherein the exposed surface is configured to contact a wafer for heating, and wherein the second surface faces the first surface of the heater substrate;

wherein the wafer heater assembly is configured for use in fabricating semiconductor chips and for in-situ cleaning with halogen gases.

17 . The wafer heater assembly of claim 16 , wherein the non-porous outermost layer is adjacent the first surface of the heater substrate.

18 . The wafer heater assembly of claim 16 , wherein the assembly comprises an interposing layer, wherein the interposing layer is disposed between the non-porous outermost layer and the heater substrate.

19 . The wafer heater assembly of claim 16 , wherein the non-porous outermost layer and the heater substrate further include an interface therebetween, and wherein the interface comprises not greater than 1 volume percent porosity.

Assignments (5)
TERMINATION AND RELEASE OF CONFIRMATORY GRANT OF SECURITY INTEREST IN PATENTS Recorded Oct 29, 2025
From: JPMORGAN CHASE BANK, N.A.
To: COORSTEK, INC.
Reel/Frame 073414/0270 →
SECURITY INTEREST Recorded Oct 28, 2025
From: COORSTEK, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 072705/0315 →
SECURITY INTEREST Recorded Nov 23, 2022
From: COORSTEK, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 061860/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2022
From: DIVAKAR, RAMESH; SIMPSON, MATTHEW
To: COORSTEK, INC.
Reel/Frame 059018/0679 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2022
From: FILER, ALAN
To: COORSTEK, INC.
Reel/Frame 059018/0739 →
Continuity (3)
Provisional Application 62908441 · Sep 30, 2019
Provisional Application 62869388 · Jul 1, 2019
Related Publication 20210005480A1 · Jan 7, 2021
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