Sampling circuit
A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.
1. A sampling circuit comprising:
a metal oxide semiconductor (MOS) transistor comprising, between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor, a third metallization receiving a reference voltage.
2. The circuit of claim 1 , wherein the third metallization has a length shorter than or equal to the length of a gate stack of the transistor.
3. The circuit of claim 1 , wherein the third metallization has the same length as a gate stack of the transistor.
4. The circuit of claim 1 , wherein the third metallization has a length equal to half the length of a gate stack of the transistor.
5. The circuit of claim 1 , wherein the third metallization has a length equal to approximately 20% of the length of a gate stack of the transistor.
6. The circuit of claim 1 , wherein the third metallization comprises at least two non-contiguous portions.
7. The circuit of claim 6 , wherein the third metallization comprises two non-contiguous portions.
8. The circuit of claim 6 , wherein the portions of the third metallization have a length equal to approximately 20% of the length of a gate stack of the transistor.
9. The circuit of claim 1 , wherein the reference voltage is a ground potential.
10. An analog to digital converter comprising:
a sampling circuit to convert an analog signal into discrete series of values, the sampling circuit comprising a field effect transistor comprising:
a source region,
a drain region,
a channel region disposed between the source region and the drain region,
a gate stack disposed over the channel region;
an insulating layer disposed over the gate stack;
a first via coupling the source region;
a first metal line disposed over the insulating layer and electrically coupled to the first via;
a second via coupling the drain region;
a second metal line disposed over the insulating layer and electrically coupled to the second via; and
a third metal line disposed over the insulating layer, the first metal line, the second metal line, and the third metal line being at a same metallization layer, the third metal line being shorter in length than the first metal line and the second metal line.
11. The circuit of claim 10 , wherein the third metallization has a length shorter than or equal to the length of the gate stack of the transistor.
12. The circuit of claim 10 , wherein the third metallization has the same length as a gate stack of the transistor.
13. The circuit of claim 10 , wherein the third metallization has a length equal to half the length of the gate stack of the transistor.
14. The circuit of claim 10 , wherein the third metallization has a length equal to approximately 20% of the length of the gate stack of the transistor.
15. The circuit of claim 10 , wherein the third metallization comprises at least two non-contiguous portions.
16. The circuit of claim 15 , wherein the third metallization comprises two non-contiguous portions.
17. The circuit of claim 15 , wherein the portions of the third metallization have a length equal to approximately 20% of the length of the gate stack of the transistor.
18. The circuit of claim 10 , wherein the third metal line is electrically coupled to a reference potential node.
19. The circuit of claim 18 , wherein the reference potential node is a ground potential node.
20. A method of converting an analog signal to a digital signal, the method comprising:
converting the analog signal into discrete series of values at a sampling circuit, the sampling circuit comprising a field effect transistor comprising:
a source region,
a drain region,
a channel region disposed between the source region and the drain region,
a gate stack disposed over the channel region;
an insulating layer disposed over the gate stack;
a first via coupling the source region;
a first metal line disposed over the insulating layer and electrically coupled to the first via;
a second via coupling the drain region;
a second metal line disposed over the insulating layer and electrically coupled to the second via; and
a third metal line disposed over the insulating layer and electrically coupled to a reference potential node, the first metal line, the second metal line, and the third metal line being at a same metallization layer, the third metal line being shorter in length than the first metal line and the second metal line.