IP Library Granted Patent US 11,449,252
Granted Patent B2
US 11,449,252 · App. 16/923,655 · Granted Sep 20, 2022

Method of writing and reading data in an NVM using Lpage identification headers

Inventor: Earl T. Cohen (Oakland, CA)
Assignee: Seagate Technology LLC
G06F3/0638G06F3/064G06F3/0608G06F3/0679G06F12/0246G06F12/1009G06F2212/7201
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Quick Facts
Patent No.
US 11,449,252
App. No.
16/923,655
Granted
Sep 20, 2022
Kind
B2
Abstract

A method includes the steps of storing non-header data into a plurality of logical pages (“Lpages”) of a non-volatile memory (“NVM”), each Lpage including a number of read units, wherein at least one of the read units is a spanning read unit that spans Lpage boundaries and includes a first byte of at least one Lpage starting in the read unit, storing, in each of the at least one spanning read units that include the first byte of the at least one Lpage starting in the read unit, an Lpage identification header per each of the at least one Lpages starting in the spanning read unit, each Lpage identification header identifying a location of the first byte of the respective Lpage starting within the respective spanning read unit, and locating an Lpage of data stored in the NVM by referring to an entry stored a flash memory controller map table.

Claims (12)

1. A method, comprising the steps of:

storing non-header data into a plurality of logical pages (“Lpages”) of a non-volatile memory (“NVM”), each Lpage including a first integer number of read units, each read unit comprising a second integer number of bytes of data that define a finest granularity, which is readable with error correction, of the NVM;

wherein at least one of the read units is a spanning read unit that spans Lpage boundaries and includes a first byte of at least one Lpage starting in the read unit;

storing, in each of the at least one spanning read units that includes the first byte of the at least one Lpage starting in the read unit, an Lpage identification header per each of the at least one Lpages starting in the spanning read unit, each Lpage identification header identifying a location of the first byte of the respective Lpage starting within the respective spanning read unit;

associating, by a map of a flash memory controller, logical block addresses (“LBAs”) of a host with respective NVM logical page numbers (“LPNs”), each LPN specifying a read unit address for a respective spanning read unit in which an Lpage identification header is stored for a respective Lpage, each LPN further specifying encoded length information indicating a span, in a number of read units, of the respective Lpage and a length of non-header data corresponding to the respective Lpage;

storing, in a table of the map, a map entry including the read unit address and the encoded length information for each LPN associated with a corresponding LBA; and

locating an Lpage of data stored in the NVM by referring to a map entry in the table, that containing an LPN specifying the read unit address of the Lpage and the encoded length information of the Lpage, and decoding the encoded length information.

2. The method of claim 1 , wherein the flash memory controller is a Solid-State Disk/Drive (SSD) controller.

3. The method of claim 1 , wherein the flash memory controller is a computing-host flash memory controller.

4. The method of claim 1 , wherein the step of associating is performed through fixed-size mapping, such that a quantum of host data is mapped to a same quantum of non-header data stored in the NVM.

5. The method of claim 1 , wherein the associating step is performed through variable-sized mapping, such that a quantum of host data is mapped to an amount of non-header data stored in the NVM that is less than the quantum of host data.

6. The method of claim 5 , wherein the variable-sized mapping is performed in granularities ranging from one byte to one-half of a read unit. .