Mitigating interference between commands for different access requests in LPDDR4 memory system

1. A command control system in LPDDR4, comprising:

a setting circuit configured to

receive a first access request and a second access request for access to a storage device, and

set an output timing of a first RAS command and an output timing of a first CAS command for the first access request and set an output timing of a second RAS command and an output timing of a second CAS command for the second access request in accordance with a clock signal at which a cycle is repeated; and

an adjuster circuit configured to adjust the output timing of the first CAS command and the output timing of the second RAS command,

the second RAS command having a command length corresponding to a multiple of a length of the cycle,

the adjuster circuit being configured to, when the output timing of the second RAS command is set in a first cycle time period which is the cycle starting from a reference time point, determine whether or not the second RAS command is output to the storage device in the first cycle time period in accordance with whether or not the output timing of the first CAS command is set in a second cycle time period constituted by a prescribed number of the cycles subsequent to the reference time point.

2. The command control system of claim 1 , wherein

the setting circuit is configured to output, to the adjuster circuit,

first information representing whether or not the output timing of the second RAS command is set in the first cycle time period, and

second information representing whether or not the output timing of the first CAS command is set in the second cycle time period.

3. The command control system of claim 1 , wherein

the prescribed number is a number larger by one than a value obtained by dividing by the length of the cycle a maximum length of the command length of the second RAS command.

4. The command control system of claim 1 , wherein

the cycle which is in the second cycle time period and in which the output timing of the first CAS command is set is a third cycle time period, and

the adjuster circuit is configured to, when the output timing of the second RAS command is set in the first cycle time period, determine whether or not the second RAS command is output to the storage device in the first cycle time period based on a location of the third cycle time period in the second cycle time period.

5. The command control system of claim 1 , wherein

the second RAS command has a command length m times as long as the length of the cycle, where m is a natural number larger than or equal to two, and

the adjuster circuit is configured to, when the output timing of the second RAS command is set in the first cycle time period and the output timing of the first CAS command is set in at least one cycle of the cycles up to an mth cycle counted from the reference time point in the second cycle time period, change the output timing of the second RAS command from the first cycle time period to a fourth cycle time period which is a cycle starting from an output end time point of the first CAS command whose output timing is set to a last cycle of the at least one cycle.

6. The command control system of claim 1 , wherein

the second RAS command has a command length m times as long as the length of the cycle, where m is a natural number larger than or equal to two, and

the adjuster circuit is configured to, when the output timing of the second RAS command is set in the first cycle time period and the output timing of the first CAS command is set in at least one cycle of the cycles up to an mth cycle counted from the reference time point in the second cycle time period, change the output timing of the first CAS command set in the at least one cycle to a cycle at or after an output end time point of the second RAS command.

7. The command control system of according to claim 1 , wherein

the second RAS command has a command length m times as long as the length of the cycle, where m is a natural number larger than or equal to two, and

the adjuster circuit is configured to, when the output timing of the second RAS command is set in the first cycle time period and the output timing of the first CAS command is set in none of cycles up to an mth cycle counted from the reference time point in the second cycle time period, output the second RAS command to the storage device in the first cycle time period.

8. The command control system of claim 1 , wherein

the adjuster circuit includes a switch configured to selectively switch between a first priority mode and a second priority mode,

in the first priority mode, when the adjuster circuit adjusts the output timing of the first CAS command and the output timing of the second RAS command, the adjuster circuit forgoes changing the output timing of the first CAS command and changes the output timing of the second RAS command from the cycle set by the setting circuit to the cycle starting from the output end time point of the first CAS command, and

in the second priority mode, when the adjuster circuit adjusts the output timing of the first CAS command and the output timing of the second RAS command, the adjuster circuit forgoes changing the output timing of the second RAS command and changes the output timing of the first CAS command from the cycle set by the setting circuit to the cycle starting from the output end time point of the second RAS command.

9. A vehicle, comprising:

the command control system of claim 1 ; and

a vehicle body equipped with the command control system.

10. A command control method in LPDDR4, comprising:

receiving a first access request and a second access request for access to a storage device, and

setting an output timing of a first RAS command and an output timing of a first CAS command for the first access request and setting an output timing of a second RAS command and an output timing of a second CAS command for the second access request in accordance with a clock signal at which a cycle is repeated; and

adjusting the output timing of the first CAS command and the output timing of the second RAS command,

the second RAS command having a command length corresponding to a multiple of a length of the cycle,

wherein, the adjusting includes, when the output timing of the second RAS command is set in a first cycle time period starting from a reference time point, determining whether or not the second RAS command is output to the storage device in the first cycle time period in accordance with whether or not the output timing of the first CAS command is set in a second cycle time period constituted by a prescribed number of the cycles subsequent to the reference time point.

11. A non-transitory computer-readable medium on which a program configured to cause at least one processor to execute the command control method of claim 10 is recorded.