System and method for low jitter phase-lock loop based frequency synthesizer

1. A phase-lock loop (PLL) based frequency synthesizer, comprising:

a first frequency divider configured to divide a reference frequency associated with an input signal V in by a factor M;

a phase frequency detector configured to generate an error voltage signal;

a charge pump configured to generate an error current signal corresponding to the error voltage signal;

a low-pass filter configured to filter the error current signal;

a voltage control oscillator (VCO), communicatively coupled to the low-pass filter, configured to generate an output signal V VCO_frac having a fractional frequency, wherein the fractional frequency is C frac times the reference frequency associated with the input signal V in , C frac being an integer or a fractional value;

a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises:

a quadrature generator configured to generate a plurality of phase shifted signals from the output signal V VCO_frac ,

an input conditioner configured to perform wave shaping of the plurality of phase shifted signals;

a phase rotator, wherein the phase rotator is configured to:

receive a wave shaped plurality of phase shifted signals;

provide positive or negative phase shifts to the wave shaped plurality of phase shifted signals in accordance with a control signal;

generate a rotation frequency in accordance with the positive or negative phase shifts provided to the wave shaped plurality of phase shifted signals;

provide an updated output signal V VCO_int having an integer frequency closest to the fractional frequency by removing the rotational frequency from the output signal V VCO_frac having the fractional frequency;

a current mode logic (CML) to complementary metal-oxide-semiconductor (CMOS) converter configured to receive CML differential voltage levels associated with the updated output signal V VCO_int and convert CML differential voltage levels to CMOS compatible voltage levels; and

a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector configured to divide the integer frequency associated with the updated output signal V VCO_int by a factor N a ×N b , wherein, N a and N b are feedback division ratios associated with the second frequency divider and provides a difference signal V diff to the phase frequency detector.

2. The PLL based frequency synthesizer of claim 1 , wherein the CIVIL to CMOS converter comprises three AC coupled stages.

3. The PLL based frequency synthesizer of claim 2 , wherein the first AC coupled stage further comprises a first capacitor, a second capacitor, a first inverter, a second inverter, a first resistive feedback and a second resistive feedback, wherein the first resistive feedback and the second resistive feedback are adjustable.

4. The PLL based frequency synthesizer of claim 2 , wherein the second AC coupled stage is configured to perform correction of the duty cycle associated with the CIVIL differential voltage levels associated with the updated output signal V VCO_int .

5. The PLL based frequency synthesizer of claim 4 , wherein the AC coupled stage further comprises a third capacitor, a fourth capacitor, a third inverter, a fourth inverter, a third resistive feedback and a fourth resistive feedback, wherein the third resistive feedback and the fourth resistive feedback are adjustable.

6. The PLL based frequency synthesizer of claim 2 , wherein the third AC coupled stage is configured to provide amplitude amplification to the output of the second stage of the CML to CMOS converter.

7. The PLL based frequency synthesizer of claim 1 , wherein the quadrature generator is a divider by two based quadrature generator.

8. The PLL based frequency synthesizer of claim 1 , wherein the quadrature generator is an all path quadrature generator.

9. The PLL based frequency synthesizer of claim 1 , wherein the quadrature generator is a poly-phase filter based quadrature generator.

10. The PLL based frequency synthesizer of claim 1 , wherein the quadrature generator is a RC ladder network based quadrature generator.

11. The PLL based frequency synthesizer of claim 1 , wherein the quadrature generator is a LC ladder network based quadrature generator.

12. The PLL based frequency synthesizer of claim 1 , wherein the input conditioner configured to change the wave shape the plurality of phase shifted signals to triangular waves.

13. The PLL based frequency synthesizer of claim 1 , wherein the control signal is generated by a phase interpolator (PI) controller.

14. The PLL based frequency synthesizer of claim 13 , wherein the PI controller further comprises:

a frequency-to-phase converter configured to receive a frequency control word (FCW) and convert a frequency associated with the associated with the FCW to a phase;

a Delta-Sigma modulator (DSM) configured to generate a step signal in accordance with the FCW;

a sub-step calculator configured to generate sub-step signals corresponding to the step signal;

a parallel to serial converter configured to receive sub-step signals in parallel and convert the parallel sub-step signals into a serial signal representing the control signal.

15. The PLL based frequency synthesizer of claim 14 , further comprising a third frequency divider.

16. The PLL based frequency synthesizer of claim 15 ,

wherein the third frequency divider is configured to divide the fractional frequency by a first factor K 1 and a second factor K 2 , wherein the second factor K 2 is greater than the first factor K 1 .

17. The PLL based frequency synthesizer of claim 16 , the DSM is further configured to operate on a clock frequency equals to the fractional frequency divided by the first factor K 1 .

18. The PLL based frequency synthesizer of claim 16 , the parallel to serial converter is further configured to operate on a clock frequency equals to the fractional frequency divided by the first second factor K 2 .

19. The PLL based frequency synthesizer of claim 1 , wherein the rotation frequency is based on a difference between the fractional frequency and the integer frequency.

20. A method for synthesizing fractional frequency comprising:

dividing, by a first frequency divider, a reference frequency associated with an input signal V in by a factor M;

generating, by a phase frequency detector, an error voltage signal;

generating, by a charge pump, an error current signal corresponding to the error voltage signal;

filtering, by a low-pass filter, the error current signal;

generating, by a voltage control oscillator (VCO), an output signal V VCO_frac having a fractional frequency, wherein the fractional frequency is C frac times the reference frequency associated with the input signal V in , C frac being an integer or a fractional value;

generating, by a quadrature generator, a plurality of phase shifted signals from the output signal V VCO_frac ;

performing, by an input conditioner, wave shaping of the plurality of phase shifted signals;

receiving, by a phase rotator, wave shaped plurality of phase shifted signals;

providing, by the phase rotator, positive or negative phase shifts to the wave shaped plurality of phase shifted signals in accordance with a control signal;

generating, by the phase rotator, a rotation frequency in accordance with the positive or negative phase shifts provided to the wave shaped plurality of phase shifted signals;

providing, by the phase rotator, an updated output signal V VCO_int having an integer frequency closest to the fractional frequency by removing the rotational frequency from the output signal V VCO_frac having the fractional frequency;

receiving, by a current mode logic (CML) to complementary metal-oxide-semiconductor (CMOS) converter, CIVIL differential voltage levels associated with the updated output signal V VCO_int ;

converting, by the CML to CMOS converter, CML differential voltage levels to CMOS compatible voltage levels;

dividing, by a second frequency divider, the integer frequency associated with the updated output signal V VCO_int by a factor N a ×N b , wherein, N a and N b are feedback division ratios associated with the second frequency divider; and

providing, by the second frequency divider, a difference signal V diff to the phase frequency detector.