Interface trap charge density reduction
The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
1. A method, comprising:
forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material;
depositing a semiconductor nitride liner over the substrate and sidewalls of the first fin and the second fin;
forming an isolation feature over the semiconductor nitride liner and between the first fin and the second fin;
after the forming of the isolation feature, epitaxially depositing a silicon cap layer along the sidewalls of the first fin and the second fin using a silicon-containing source gas; and
annealing the silicon cap layer at a first temperature while at least a portion of the silicon cap layer is exposed.
2. The method of claim 1 , wherein the first fin comprises a p-type channel region, wherein the second fin comprises an n-type channel region, wherein the first semiconductor material comprises germanium, wherein the second semiconductor material comprises silicon.
3. The method of claim 1 , wherein the epitaxially depositing of the silicon cap layer comprises use of silane (SiH 4 ), silicon tetrachloride (SiC 14 ), trichlorosilane (TCS), or dichlorosilane (SiH 2 C 12 ).
4. The method of claim 1 , wherein the first temperature is greater than 800 ° C.
5. The method of claim 1 , wherein the first temperature is between about 800 ° C. and about 1050 ° C.
6. The method of claim 1 , wherein the epitaxially depositing of the silicon cap layer comprises depositing silicon using atomic layer deposition (ALD).
7. The method of claim 1 , wherein the annealing of the silicon cap layer increases crystallinity of the silicon cap layer.
8. The method of claim 1 , wherein the forming of the isolation feature comprises:
blanketly depositing a dielectric layer over the semiconductor nitride liner;
planarizing the dielectric layer to expose the first fin and the second fin; and
etching back the dielectric layer to form the isolation feature such that a portion of the first fin and a portion of the second fin rise above the isolation feature.
9. The method of claim 1 , further comprising:
after the annealing, depositing an interfacial layer over the silicon cap layer; and
forming a polysilicon dummy gate stack over the interfacial layer, wherein the interfacial layer comprises silicon oxide.
10. A method, comprising:
forming, on a substrate, a first fin comprising silicon and germanium;
forming, on the substrate, a second fin comprising silicon;
forming a silicon cap layer over the first fin and the second fin;
performing a first anneal at a first temperature and a first pressure while at least a portion of the silicon cap layer is exposed;
forming source/drain features over source/drain regions of the first fin and the second fin;
forming a gate structure over channel regions of the first fin and the second fin; and
after the forming of the gate structure, performing a second anneal at a second temperature and a second pressure while no portion of the silicon cap layer is exposed;
wherein the first temperature is greater than the second temperature,
wherein the second pressure is greater than the first pressure.
11. The method of claim 10 , wherein a germanium content in the first fin is between about 20 % and about 60 %.
12. The method of claim 10 , wherein the forming of the silicon cap layer comprises depositing silicon using atomic layer deposition (ALD).
13. The method of claim 10 , wherein the forming of the silicon cap layer comprises epitaxially growing silicon over the first fin and the second fin.
14. The method of claim 10 , wherein the first temperature is between about 800 ° C. and about 1050 ° C., wherein the first pressure is between about 0 . 01 atmosphere (atm) and about 1 . 1 atm.
15. The method of claim 10 , wherein the second temperature is between about 350 ° C. and about 450 ° C., wherein the second pressure is between about 10 atmosphere (atm) and about 20 atm.
16. The method of claim 10 , wherein the gate structure comprises a high-k dielectric layer, a work function layer, and a metal fill layer.
17. A method, comprising:
forming, on a substrate, a first fin comprising silicon and germanium;
forming, on the substrate, a second fin comprising silicon;
forming an isolation feature over the substrate and between the first fin and the second fin;
after the forming of the isolation feature, forming a silicon cap layer over the first fin and the second fin; after the forming of the silicon cap layer, performing a first anneal at a temperature between about 800 ° C. and about 1050 ° C.;
forming a gate structure over channel regions of the first fin and the second fin; and
after the forming of the gate structure, performing a second anneal at a temperature between about 350 ° C. and about 450 ° C.
18. The method of claim 17 , wherein the forming of the silicon cap layer comprises depositing silicon using atomic layer deposition (ALD).
19. The method of claim 17 , wherein the forming of the silicon cap layer comprises epitaxially growing silicon over the first fin and the second fin.
20. The method of claim 8 , wherein the forming of the isolation feature comprises:
after the etching back, selectively removing the semiconductor nitride liner above the isolation feature.