IP Library Granted Patent US 11,556,149
Granted Patent B2
US 11,556,149 · App. 16/927,480 · Granted Jan 17, 2023

Systems and methods of forming a video display

Inventors: Dan Odell Boice (Taipei, TW); Yu-Lung Lin (Chungli, TW); Yi-Fan Wang (Taipei, TW); Chao-Kai Huang (Taipei County, TW)
Assignee: Dell Products, LP
G06F1/1637H01L51/5237H05K1/147H05K1/189G06F1/203H05K2201/056H05K2201/10128
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Quick Facts
Patent No.
US 11,556,149
App. No.
16/927,480
Granted
Jan 17, 2023
Kind
B2
Abstract

An information handling system may include an organic light-emitting diode (OLED) display layer of a video display to display an image to a user; an A-cover forming a housing behind the OLED display layer; and a physically bifurcated display daughter board between the OLED display layer and the A-cover, the physically bifurcated display daughter board including: a first portion of the display daughter board including a source driver integrated circuit (IC) operatively coupled to a processor to receive graphics data; and a second portion of the display daughter board comprising a power management integrated circuit (PMIC) operatively coupled to the first portion and a power source; the second portion of the display daughter board being mechanically coupled to an interior surface of the A-cover to dissipate heat away from the OLED display layer.

Claims (39)

1. An information handling system, comprising:

an organic light-emitting diode (OLED) display layer of a video display to display an image to a user;

an A-cover forming a housing behind the OLED display layer; and

a physically bifurcated display daughter board between the OLED display layer and the A-cover, the physically bifurcated display daughter board including:

a first portion of the display daughter board including a source driver integrated circuit (IC) operatively coupled to a processor to receive graphics data; and

a second portion of the display daughter board comprising a power management integrated circuit (PMIC) operatively coupled to the first portion of the display daughter board and a power source,

where the second portion of the display daughter board is mechanically coupled to an interior surface of the A-cover to dissipate heat away from the OLED display layer.

2. The information handling system of claim 1 , wherein the first portion of the display daughter board is mechanically coupled to a back surface of the OLED display layer.

3. The information handling system of claim 1 , wherein the first portion of the display daughter board and the second portion of the display daughter board are electrically and communicatively coupled via a flexible flat cable (FFC).

4. The information handling system of claim 1 , further comprising a bezel cover formed around the OLED display layer as part of a B-cover of the video display, the bezel comprising a four-sided narrow border around the edges of the OLED display layer.

5. The information handling system of claim 1 , wherein the first portion of the display daughter board is electrically coupled to the OLED display layer via a flexible flat cable (FFC) in a bent-type configuration.

6. The information handling system of claim 1 , wherein the A-cover is made of a thermo conductive material that conducts heat from the PMIC and out of a back surface of the A-cover and away from the OLED display layer.

7. The information handling system of claim 1 , wherein the PMIC receives power from the power source that is a battery to provide managed power to the first portion of the display daughter board and OLED display layer.

8. The information handling system of claim 1 , wherein the second portion of the display daughter board is mechanically coupled to an interior surface of the A-cover via a thermally conductive adhesive.

9. An information handling system, comprising:

a processor;

a memory;

a video display including an organic light-emitting diode (OLED) display layer to display an image to a user;

an A-cover forming a display housing behind the OLED display layer; and

a physically bifurcated display daughter board between the OLED display layer and the A-cover, the physically bifurcated display daughter board including:

a first portion of the display daughter board operatively coupled to a back surface of the OLED display layer via a first flexible flat cable (FFC) in a bent-type configuration, the first portion of the display daughter board including a source driver integrated circuit (IC) operatively coupled to a processor to receive graphics data; and

a second portion of the display daughter board comprising a power management integrated circuit (PMIC), the second portion of the display daughter board being operatively coupled to the first portion and a power source, where

the second portion of the display daughter board is mechanically coupled to an interior surface of the A-cover to dissipate heat away from the OLED display layer.

10. The information handling system of claim 9 , wherein the processor, memory, and power source are disposed in a base chassis operatively and electrically coupled to the display housing via a hinge including power and communication lines.

11. The information handling system of claim 9 , wherein the first portion of the display daughter board and the second portion of the display daughter board are electrically and communicatively coupled via a second FFC.

12. The information handling system of claim 9 , wherein the A-cover is made of a thermo conductive material that conducts heat from the PMIC and out of a back surface of the A-cover and away from the OLED display layer.

13. The information handling system of claim 9 , wherein the PMIC receives power from the power source to provide managed power to the first portion of the display daughter board and the OLED display layer.

14. The information handling system of claim 9 , wherein the second portion of the display daughter board is mechanically coupled to an interior surface of the A-cover via an adhesive and disposed above the first portion of the display daughter board in the display housing.

15. The information handling system of claim 9 , further comprising a bezel cover formed around the OLED display layer as part of a B-cover of the video display, the bezel comprising a four-sided narrow border of equal width around the edges of the OLED display layer.

16. An information handling system, comprising:

an organic light-emitting diode (OLED) display layer to display an image to a user;

a physically bifurcated display daughter board between the OLED display layer and the A-cover, the physically bifurcated display daughter board including:

a first portion of the display daughter board including a source driver integrated circuit (IC) operatively coupled to a processor to receive graphics data; and

a second portion of the display daughter board comprising a power management integrated circuit (PMIC) operatively coupled to the first portion of the display daughter board and a power source, where

the second portion of the display daughter board is mechanically coupled to a back surface of the OLED display layer disposed above the first portion of the daughter board in a display housing to dissipate heat created by the PMIC apart from the first portion of the display daughter board.

17. The video display of claim 16 , wherein the first portion of the display daughter board is mechanically coupled to a back surface of the OLED display layer.

18. The video display of claim 16 , wherein the first portion of the display daughter board and the second portion of the display daughter board are electrically and communicatively coupled via a flexible flat cable (FFC).

19. The video display of claim 16 , further comprising a bezel cover formed around the OLED display layer as part of a B-cover of the video display, the bezel comprising a four-sided narrow border of equal width around the edges of the OLED display layer.

20. The video display of claim 16 , wherein the second portion of the display daughter board is mechanically coupled to the OLED display layer via a thermal insulator layer to reduce application of heat from the PMIC to the OLED layer.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053574/0221) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060333/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053578/0183) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060332/0864 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053573/0535) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060333/0106 →
RELEASE OF SECURITY INTEREST AT REEL 053531 FRAME 0108 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0371 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053578/0183 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053573/0535 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053574/0221 →
SECURITY AGREEMENT Recorded Aug 18, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 053531/0108 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: ODELL BOICE, DAN; LIN, YU-LUNG; WANG, YI-FAN; HUANG, CHAO-KAI
To: DELL PRODUCTS, LP
Reel/Frame 053193/0209 →