Secure chips with serial numbers
An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a second portion of the non-common structures is adapted to store or generate a first predetermined value which uniquely identifies the first non-common circuit, wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.
1. An electronic device comprising a semiconductor chip that comprises a plurality of structures formed in the semiconductor chip:
wherein the semiconductor chip is a member of a set of semiconductor chips, wherein the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets; and
wherein the plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset are different from the non-common structures of the semiconductor chips in every other subset.
2. The electronic device of claim 1 , wherein at least a first portion of the non-common structures is adapted to store or generate a first predetermined value.
3. The electronic device of claim 2 , wherein the first predetermined value is readable from outside the semiconductor chip by automated electromagnetic, optical, or electronic reading means.
4. The electronic device of claim 2 , wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.
5. The electronic device of claim 2 , wherein the first predetermined value is readable from the structure of the first portion of the non-common structures and/or wherein the shape of the first portion of the non-common structures stores the first predetermined value.
6. The electronic device of claim 2 , wherein a first non-common circuit is formed from the first portion of the non-common structures of the semiconductor chip and a first portion of the common structures of the semiconductor chip, and wherein the circuit configuration of the first non-common circuit of the semiconductor chips of each subset is different from a circuit configuration of any of the semiconductor chips in every other subset.
7. The electronic device of claim 6 , wherein the first non-common circuit comprises at least one of:
a read-only memory circuit which is fabricated with the first predetermined value pre-stored in the read-only memory circuit;
a logic circuit, wherein the logic circuit is adapted to generate the first predetermined value.
8. The electronic device of claim 1 wherein the set of non-common structures of the semiconductor chip is different from the set of non-common structures of every other semiconductor chip of the set of the semiconductor chips.
9. The electronic device of claim 6 , wherein the electronic device comprises at least one input terminal and at least one output terminal, and the first non-common circuit is connected to the input and output terminals, and wherein the first predetermined value is electronically readable from the output terminal.
10. The electronic device of claim 6 , wherein the electronic device comprises at least one input terminal for receiving a challenge and at least one output terminal for outputting a response, and the first non-common circuit forms a challenge-response circuit connected to the at least one input terminal and the at least one output terminal,
wherein the challenge-response circuit is adapted for generating a response at the at least one output terminal based on a challenge applied to the at least one input terminal, the challenge and the response having a predetermined relationship.
11. The electronic device of claim 10 , wherein the response generated by the challenge-response circuit depends on both the challenge applied to the at least one input terminal and the first predetermined value.
12. The electronic device of claim 1 , wherein the plurality of structures are formed on three or more layers of the semiconductor chip, including one or more non-common layers containing the non-common structures, and at least one common layer above the one or more non-common layers, the at least one common layer containing common structures but no non-common structures.
13. The electronic device of claim 12 , wherein all of the non-common structures are formed in only one layer of the semiconductor chip.
14. The electronic device of claim 12 , wherein the semiconductor chip comprises at least a second common layer below the one or more common layers, the second common layer containing common structures but no non-common structures.
15. The electronic device of claim 1 , wherein the plurality of structures are formed in a plurality of layers of the semiconductor chip, and the non-common structures include at least one of: connections between metal layers of the plurality of layers; connections between a metal layer and a gate in a contact layer of the plurality of layers; connections in a local interconnect layer of the plurality of layers; and a P- or N-doped diffusion region of a transistor or diode of one of the plurality of layers.
16. The electronic device of claim 12 , wherein the non-common structures of the one or more common layers are formed using a charged particle multi-beamlet lithography system, and the common layers are formed using a mask-based lithography process.
17. The electronic device of claim 1 , wherein the set of semiconductor chips are all formed from a single wafer.
18. The electronic device of claim 2 , wherein the first predetermined value of the semiconductor chip is different from a predetermined value of every other semiconductor chip of the set of the semiconductor chips.
19. The electronic device of claim 1 , wherein the set of common structures and the set of non-common structures of the semiconductor chip are interconnected to form one or more electronic circuits.
20. The electronic device of claim 6 , wherein a second non-common circuit is formed from a second portion of the non-common structures of the semiconductor chip and a second portion of the common structures of the semiconductor chip, and wherein the first predetermined value of the semiconductor chip has a value that uniquely identifies the second non-common circuit.