Low leakage FET
FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function Φ MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function Φ MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.
1. An integrated circuit fabricated on a silicon-on-insulator substrate and including at least one low-leakage field effect transistor (FET) that includes:
(a) a gate structure having central and edge regions each having its own associated work function Φ MF ;
(b) a central conduction channel defined by the gate structure, the central conduction channel having a threshold voltage Vt C and a length L; and
(c) at least one edge transistor defined by a corresponding edge region of the gate structure, each edge transistor having a threshold voltage Vt E determined in part by the work function Φ MF of the corresponding edge region of the gate structure;
wherein the work function Φ MF of at least one corresponding edge region of the gate structure is modified sufficiently to increase the Vt E of such corresponding edge transistor to be approximately equal to or greater than Vt C .
2. The invention of claim 1 , wherein at least one FET is an NMOSFET and the work function Φ MF of the corresponding edge regions of the gate structure is increased by the presence of a P dopant within a P implant region within such edge regions of the gate structure.
3. The invention of claim 2 , wherein the P implant region has a length L P less than or equal to the length L.
4. An integrated circuit fabricated on a silicon-on-insulator substrate and including at least one low-leakage field effect transistor (FET) that includes:
(a) a gate structure having a center length L, the gate structure having central and edge regions each having its own associated work function Φ MF ;
(b) source and drain regions defined by the gate structure;
(c) a central conduction channel between the source and drain regions, the central conduction channel having a threshold voltage Vt C ; and
(d) at least one edge transistor defined by a corresponding edge region of the gate structure, each edge transistor having a threshold voltage Vt E determined in part by the work function Φ MF of the corresponding edge region of the gate structure;
wherein the work function Φ MF of at least one corresponding edge region of the gate structure is modified sufficiently to increase the Vt E of such corresponding edge transistor to be approximately equal to or greater than Vt C .
5. The invention of claim 4 , wherein at least one FET is an NMOSFET.
6. The invention of claim 5 , wherein the work function Φ MF of the corresponding edge regions of the gate structure is increased by the presence of a P dopant within a P implant region within such edge regions of the gate structure.
7. The invention of claim 6 , wherein the P implant region has a length L P less than or equal to the length L.
8. The invention of claim 6 , wherein the source and drain regions are encompassed by a masked implant area having a shape that approximately conforms to the shape of the P implant region within such edge regions.
9. The invention of claim 8 , wherein the P implant region within such edge regions is rectangular or triangular shaped.
10. The invention of claim 5 , wherein the gate structure includes an N+ polysilicon layer and the work function Φ MF of the corresponding edge regions of the gate structure is increased by the presence of a P+ dopant within the N+ polysilicon layer of such edge regions.
11. The invention of claim 5 , wherein the gate structure includes an N+ polysilicon layer and further including at least one P+ implant region formed within at least a portion of the gate structure and over a portion of the at least one edge transistor, wherein the work function Φ MF of the corresponding edge regions of the gate structure is increased by the presence of the overlying at least one P+ implant region.
12. The invention of claim 4 , wherein at least one FET is a PMOSFET.
13. The invention of claim 4 , wherein the at least one edge region of the gate structure is flared to a length L + greater than the length L.
14. The invention of claim 4 , wherein the increase in the work function Φ MF and Vt E is at least about 0.3 V.
15. The invention of claim 4 , wherein a current leakage of at least one edge transistor with the increased work function Φ MF is at least about 10 times less than the current leakage of such edge transistor without the increased work function Φ MF .
16. The invention of claim 4 , wherein the FET further includes a body tie to one of the source region, the gate structure, or an external node.
17. The invention of claim 4 , wherein the work function Φ MF of the corresponding edge regions of the gate structure is increased by the presence of a metal or metal-like region within the edge regions of the gate structure such that the work function Φ MF differs between the central and edge regions of the gate structure.
18. The invention of claim 4 , wherein the work function Φ MF of the corresponding edge portions of the gate structure is increased by forming the central region of the gate structure with a first metal or metal-like material, and forming the edge regions of the gate structure with a second metal or metal-like material, such that the work function Φ MF differs between the central and edge regions of the gate structure.
19. The invention of claim 4 , wherein the gate structure is formed of polysilicon, and the work function Φ MF of the corresponding edge portions of the gate structure is increased by the presence of a dopant within the edge regions of the gate structure to form degeneratively-doped polysilicon, such that the work function Φ MF differs between the central and edge regions of the gate structure.
20. The invention of claim 4 , wherein the work function Φ MF of the corresponding edge portions of the gate structure is increased by the presence of a dopant within an insulator beneath the gate structure, such that the work function Φ MF differs between the central and edge regions of the gate structure.
21. The invention of claim 4 , wherein the work function Φ MF of the corresponding edge portions of the gate structure is increased by forming the central region of the gate structure from a material having a first dopant, and modifying the edge regions of the gate structure with a second dopant, such that the work function Φ MF differs between the central and edge regions of the gate structure.