IP Library Granted Patent US 11,011,979
Granted Patent B2
US 11,011,979 · App. 16/930,983 · Granted May 18, 2021

Booster circuit

Inventor: Fumiyasu Utsunomiya (Tokyo, JP)
Assignee: ABLIC INC.
H02M3/07
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Quick Facts
Patent No.
US 11,011,979
App. No.
16/930,983
Granted
May 18, 2021
Kind
B2
Abstract

Provided is a booster circuit capable of adjusting a power conversion capacity in accordance with input power and also of stably performing a boost operation. The booster circuit includes a first voltage detection circuit configured to output as a first control signal a result of comparing an input voltage and a first voltage obtained by dividing an output voltage, a first oscillation circuit configured to be controlled to operate based on the first control signal, and a first switched-capacitor booster circuit configured to operate in accordance with a first clock signal provided from the first oscillation circuit.

Claims (10)

1. A booster circuit, comprising:

an input terminal to which an input voltage is applied;

an output terminal from which an output voltage is output;

a first voltage detection circuit configured to output as a first control signal a result of comparing the input voltage and a first voltage obtained by dividing the output voltage;

a first oscillation circuit configured to be controlled to operate based on the first control signal; and

a first switched-capacitor booster circuit which includes an input port connected to the input terminal and an output port connected to the output terminal and is configured to operate in accordance with a first clock signal supplied from the first oscillation circuit.

2. The booster circuit according to claim 1 , further comprising:

a second voltage detection circuit configured to output as a second control signal a result of comparing the input voltage and a second voltage obtained by dividing the output voltage, the second voltage being lower than the first voltage;

a second oscillation circuit configured to be controlled to operate based on the second control signal; and

a second switched-capacitor booster circuit configured to operate in accordance with a second clock signal supplied from the second oscillation circuit, wherein the second switched-capacitor booster circuit is configured to output a voltage higher than the output voltage to a substrate of a backflow-prevention PMOS transistor of the first switched-capacitor booster circuit.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2020
From: UTSUNOMIYA, FUMIYASU
To: ABLIC INC.
Reel/Frame 053232/0680 →
Priority Claims (2)
JP JP2019-142738 · Aug 2, 2019 · national
JP JP2020-072887 · Apr 15, 2020 · national
Continuity (1)
Related Publication 20210036606A1 · Feb 4, 2021