Optimized gate driver for low voltage power loss protection system
An integrated circuit (IC) comprises a regulator circuit, a bootstrap control circuit, and a gate driver that drives a transistor pair in buck or boost mode to switch current through an inductor. The IC has a VIN terminal coupled to receive a voltage generated from an AC power source, a STR terminal coupled to receive a voltage from a stored power source (e.g., a capacitor bank), and a HSB terminal that is capacitively coupled to the inductor. When bucking or boosting, the regulator circuit generates VDD supply voltage from the stored power source, supplies the VDD supply voltage onto the bootstrap control circuit, and the bootstrap control circuit generates a gate driver supply voltage that is supplied to the gate driver circuit. When not bucking or boosting, voltage on the HSB terminal is maintained between a voltage threshold from the AC power source without draining the stored power source.
1. An integrated circuit comprising:
a first terminal coupled to receive a first voltage generated from an alternating current (AC) power source;
a second terminal coupled to receive a second voltage generated from a storage device comprising a bank of capacitors;
a third terminal coupled to a load;
a fourth terminal capacitively coupled to a lead of an inductor; and
a gate drive circuit, wherein the gate drive circuit is configured to:
drive a pair of switching transistors configured to switch current through the inductor;
draw current primarily from the storage device when the pair of switching transistors are being driven; and
draw current primarily from the AC power source when the pair of switching transistors are not being driven.
2. The integrated circuit of claim 1 , further comprising a bootstrap control circuit configured to maintain the fourth terminal within a maximum and minimum voltage when the pair of switching transistors are not being driven.
3. The integrated circuit of claim 2 , wherein the minimum voltage is at least half the first voltage.
4. The integrated circuit of claim 2 , further comprising a regulator circuit having a first node coupled to the first terminal, a second node coupled to the second terminal, and a third node configured to supply a VDD supply voltage.
5. The integrated circuit of claim 4 , wherein the bootstrap control circuit has a first node coupled to the third node of the regulator circuit, a second node coupled to the fourth terminal, and a third node coupled to the third terminal.
6. The integrated circuit of claim 5 , wherein the second node of the bootstrap control circuit is further coupled to supply a gate driver supply voltage for driving the pair of switching transistors to the gate drive circuit.
7. The integrated circuit of claim 5 , wherein the bootstrap control circuit comprises:
a first diode having an input coupled to the first node of the bootstrap control circuit and an output coupled to the second node of the bootstrap control circuit;
a charge pump circuit having an input coupled to the third node of the bootstrap control circuit; and
a second diode having an input coupled to an output of the charge pump circuit, and wherein an output of the second diode is coupled to the second node of the bootstrap control circuit.
8. The integrated circuit of claim 7 , wherein the bootstrap control circuit further comprises a charge pump control circuit configured to generate and supply a charge pump control signal CPEN onto the charge pump circuit.
9. The integrated circuit of claim 8 , wherein the charge pump control signal CPEN is generated based in part on a voltage on the fourth terminal and a voltage on a fifth terminal of the integrated circuit, wherein the fifth terminal of the integrated circuit is coupled to the lead of the inductor.
10. The integrated circuit of claim 4 , wherein the regulator circuit comprises a low dropout (LDO) regulator.
11. The integrated circuit of claim 10 , wherein the LDO regulator comprises:
a first voltage regulator, wherein the first voltage regulator is configured to receive the first voltage from the first terminal and output a first regulated voltage; and
a second voltage regulator, wherein the second voltage regulator is configured to receive the second voltage from the second terminal and output a second regulated voltage;
wherein the LDO regulator generates the VDD supply voltage based on the first regulated voltage or the second regulated voltage.
12. The integrated circuit of claim 11 , wherein the LDO regulator further comprises:
a comparator having a first input lead configured to receive the first regulated voltage and a second input lead configured to receive the second regulated voltage; and
a multiplexer having a first input lead coupled to receive the first regulated voltage and a second input lead coupled to receive the second regulated voltage, wherein the multiplexer outputs either the first regulated voltage or second regulated voltage based on an output of the comparator.
13. The integrated circuit of claim 1 , wherein the pair of switching transistors comprises a high side transistor and a low side transistor which are operable in a mode selected from the group consisting of: a boost operating mode, and a buck operating mode when driven by the gate drive circuit.
14. The integrated circuit of claim 13 , wherein when the high side transistor and the low side transistor are not operating in either the boost operating mode or the buck operating mode, then the integrated circuit does not draw current from the storage device.
15. The integrated circuit of claim 13 , wherein when the high side transistor and the low side transistor are not operating in either the boost operating mode or the buck operating mode, a gate driver supply voltage for the gate drive circuit is maintained between a first voltage threshold and a second voltage threshold.
16. The integrated circuit of claim 15 , wherein when the high side transistor and the low side transistor transition to operating in the buck operating mode, maintaining the gate driver supply voltage between the first voltage threshold and the second voltage threshold provides a desirable transient response.