Semiconductor memory device and manufacturing method thereof

1. A semiconductor memory device comprising:

a first etch stop layer;

a source layer on the first etch stop layer;

a second etch stop layer on the source layer;

a stack structure on the second etch stop layer; and

a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer,

wherein a material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.

2. The semiconductor memory device of claim 1 , wherein the stack structure includes insulating patterns and conductive patterns that are alternately stacked,

wherein the material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the insulating patterns.

3. The semiconductor memory device of claim 1 , further comprising a base part under the first etch stop layer,

wherein a lowermost portion of the channel structure is disposed in the base part.

4. The semiconductor memory device of claim 3 , wherein the base part includes an insulating material.

5. The semiconductor memory device of claim 1 , further comprising a slit structure penetrating the stack structure and the second etch stop layer.

6. The semiconductor memory device of claim 5 , wherein a level of a lowermost portion of the slit structure is lower than that of a bottom surface of the second etch stop layer.

7. The semiconductor memory device of claim 5 , wherein the slit structure includes a common source line electrically connected to the source layer and spacers at both sides of the common source line,

wherein the spacers penetrate the second etch stop layer.

8. The semiconductor memory device of claim 1 , wherein the source layer includes an interposition part disposed between the first etch stop layer and the channel structure,

wherein the interposition part is disposed at the same level as the first etch stop layer.

9. The semiconductor memory device of claim 1 , wherein the channel structure includes a first memory layer and a second memory layer, which are spaced apart from each other by the source layer,

wherein the first memory layer is disposed at a level that is higher than the first etch stop layer, and

the second memory layer is disposed at a level that is lower than the second etch stop layer.

10. The semiconductor memory device of claim 9 , wherein the stack structure includes a conductive pattern, an insulating pattern, and a barrier layer between the conductive pattern and the insulating pattern,

wherein a portion of the barrier layer is disposed at the same level as the second etch stop layer.

11. A semiconductor memory device comprising:

a base part;

a first etch stop layer on the base part;

a source layer on the first etch stop layer;

a second etch stop layer on the source layer;

a stack structure on the second etch stop layer; and

a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure,

wherein the channel structure is electrically connected to the source layer, and

wherein a lowermost portion of the channel structure is disposed in the base part.

12. The semiconductor memory device of claim 11 , wherein the base part is an insulating layer, including a peripheral circuit device.

13. The semiconductor memory device of claim 11 , wherein the base part is a semiconductor substrate.

14. The semiconductor memory device of claim 11 , wherein the first and second etch stop layers include at least one of SiCO and SiCN.

15. The semiconductor memory device of claim 11 , wherein a material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the base part.

16. The semiconductor memory device of claim 11 , wherein a level of the lowermost portion of the channel structure is lower than that of a bottom surface of the first etch stop layer.