IP Library Granted Patent US 11,422,877
Granted Patent B2
US 11,422,877 · App. 16/932,885 · Granted Aug 23, 2022

Information processing apparatus, method, and non-transitory computer-readable storage medium for storing control program of information processing apparatus

Inventor: Tamotsu Takeuchi (Yokohama, JP)
Assignee: FUJITSU LIMITED
G06F11/0772G06F9/3836G06F11/0721
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Quick Facts
Patent No.
US 11,422,877
App. No.
16/932,885
Granted
Aug 23, 2022
Kind
B2
Abstract

A method implemented by a computer including a plurality of components, each of the plurality of components including a processor configured to output an error notification after detecting an error, the method includes: executing a first processing when the error notification is received from an error detected processor, the first processing including specifying an error component by analyzing error information from the error detected processor; executing a second processing to issue a request for active exchange when another component able to be actively exchanged with the error component exists; executing a third processing to issue instructions in response to detecting that the operating system is alive after the issuing of the request, the instructions including a deletion instruction and an addition instruction, the deletion instruction being configured to execute active deletion processing of the error component, the addition instruction being configured to execute active addition processing of the other component.

Claims (71)

1. An information processing apparatus comprising:

a plurality of components, each of the plurality of components including a processor, the processor being configured to output an error notification in response to detecting an error; and

a management circuit coupled to the plurality of components, the management circuit being configured to

execute an error specification processing when the error notification is received from an error detected processor which has detected an error occurred, the error detected processor being the processor included in any of the plurality of components, the error specification processing including specifying an error component by analyzing error information obtained from the error detected processor, the error component being any of the plurality of components and including a part that causes an error,

execute an exchange determination processing that includes issuing a request for active exchange when another component exists from among the plurality of components, the other component being a component able to be actively exchanged with the error component,

execute an existence monitoring processing that includes

monitoring whether or not an operating system executed by the information processing apparatus is alive, and

issuing instructions in response to detecting that the operating system is alive after the issuing of the request for active exchange, the instructions including a deletion instruction and an addition instruction, the deletion instruction being configured to execute active deletion processing of the error component, the addition instruction being configured to execute active addition processing of the other component, and

execute an active exchange processing that includes

initiating the active deletion processing in response to the deletion instruction issued from the existence monitoring processing, and

initiating the active addition processing in response to the active addition instruction issued from the existence monitoring processing.

2. The information processing apparatus according to claim 1 ,

wherein the exchange determination processing is configured to, when it is determined that an error occurs again during the active exchange, refrain from the issuing of the request for active exchange even when the other component that is able to be actively exchanged with the error component exists.

3. The information processing apparatus according to claim 1 ,

wherein the existence monitoring processing is configured to, during no detection that the operating system is alive, prevent from the issuing of the instructions even when the request for active exchange has been issued.

4. The information processing apparatus according to claim 1 ,

wherein the existence monitoring processing is configured to

recognize the alive operating system by an occurrence a timer associated with the alive operating system is reset in response to a timer reset command, the timer reset command being a command periodically issued from the alive operating system,

issue the instructions in response to the resetting of the timer associated with the alive operating system after when the request for active exchange has been issued.

5. The information processing apparatus according to a claim 1 ,

wherein the exchange determination processing is configured to

obtain specification information via a management bus that couples the management circuit with the plurality of components, the specification information including first specification information and second specification information, the first specification information indicating information on the processor included in the unused component from among the plurality of components, the second specification information indicating information on the processor included in the error component from among the plurality of components,

determine whether or not active exchange is able to be performed on a basis of comparison between the first specification information and the second specification information.

6. The information processing apparatus according to claim 1 ,

wherein the management circuit includes a management processor coupled to the processor included in each of the plurality of components via a management bus,

wherein the management processor is configured to execute the error specification processing, the exchange determination processing, the existence monitoring processing, and the active exchange processing.

7. The information processing apparatus according to claim 6 ,

wherein the management processor is mounted in each of the plurality of components, and

the management circuit is realized by any one of the management processors respectively mounted in the plurality of components.

8. The information processing apparatus according to claim 1 , further comprising

an input and output circuit coupled to the processor included in each of the plurality of components via an input and output bus, the input and output circuit including a predetermined number of interfaces and a storage device, the storage device being configured to store firmware to be executed by the processor included in each of the plurality of components,

the management circuit is realized by the firmware executed by the processor included in any of the plurality of components.

9. A non-transitory computer-readable storage medium for storing a control program which causes a computer to perform processing, the computer including a plurality of components and a management circuit, each of the plurality of components including a processor configured to output an error notification in response to detecting an error, the management circuit being configured to perform the processing, the processing comprising:

executing an error specification processing when the error notification is received from an error detected processor which has detected an error occurred, the error detected processor being the processor included in any of the plurality of components, the error specification processing including specifying an error component by analyzing error information obtained from the error detected processor, the error component being any of the plurality of components and including a part that causes an error;

executing an exchange determination processing that includes issuing a request for active exchange when another component exists from among the plurality of components, the other component being a component able to be actively exchanged with the error component;

executing an existence monitoring processing that includes

monitoring whether or not an operating system executed by the information processing apparatus is alive, and

issuing instructions in response to detecting that the operating system is alive after the issuing of the request for active exchange, the instructions including a deletion instruction and an addition instruction, the deletion instruction being configured to execute active deletion processing of the error component, the addition instruction being configured to execute active addition processing of the other component; and

executing an active exchange processing that includes

initiating the active deletion processing in response to the deletion instruction issued from the existence monitoring processing, and

initiating the active addition processing in response to the active addition instruction issued from the existence monitoring processing.

10. The non-transitory computer-readable storage medium according to claim 9 ,

wherein the exchange determination processing is configured to, when it is determined that an error occurs again during the active exchange, refrain from the issuing of the request for active exchange even when the other component that is able to be actively exchanged with the error component exists.

11. The non-transitory computer-readable storage medium according to claim 9 ,

wherein the existence monitoring processing is configured to, during no detection that the operating system is alive, prevent from the issuing of the instructions even when the request for active exchange has been issued.

12. The non-transitory computer-readable storage medium according to claim 9 ,

wherein the existence monitoring processing is configured to

recognize the alive operating system by an occurrence a timer associated with the alive operating system is reset in response to a timer reset command, the timer reset command being a command periodically issued from the alive operating system,

issue the instructions in response to the resetting of the timer associated with the alive operating system after when the request for active exchange has been issued.

13. The non-transitory computer-readable storage medium according to a claim 9 ,

wherein the exchange determination processing is configured to

obtain specification information via a management bus that couples the management circuit with the plurality of components, the specification information including first specification information and second specification information, the first specification information indicating information on the processor included in the unused component from among the plurality of components, the second specification information indicating information on the processor included in the error component from among the plurality of components,

determine whether or not active exchange is able to be performed on a basis of comparison between the first specification information and the second specification information.

14. The non-transitory computer-readable storage medium according to claim 9 ,

wherein the management circuit includes a management processor coupled to the processor included in each of the plurality of components via a management bus,

wherein the management processor is configured to execute the error specification processing, the exchange determination processing, the existence monitoring processing, and the active exchange processing.

15. The non-transitory computer-readable storage medium according to claim 4 ,

wherein the management processor is mounted in each of the plurality of components, and

the management circuit is realized by any one of the management processors respectively mounted in the plurality of components.

16. The non-transitory computer-readable storage medium according to claim 9 , the processing further comprising:

an input and output circuit coupled to the processor included in each of the plurality of components via an input and output bus, the input and output circuit including a predetermined number of interfaces and a storage device, the storage device being configured to store firmware to be executed by the processor included in each of the plurality of components,

the management circuit is realized by the firmware executed by the processor included in any of the plurality of components.

17. A method implemented by a computer, the computer including a plurality of components and a management circuit, each of the plurality of components including a processor configured to output an error notification in response to detecting an error, the management circuit being configured to perform the method, the method comprising:

executing an error specification processing when the error notification is received from an error detected processor which has detected an error occurred, the error detected processor being the processor included in any of the plurality of components, the error specification processing including specifying an error component by analyzing error information obtained from the error detected processor, the error component being any of the plurality of components and including a part that causes an error;

executing an exchange determination processing that includes issuing a request for active exchange when another component exists from among the plurality of components, the other component being a component able to be actively exchanged with the error component;

executing an existence monitoring processing that includes

monitoring whether an operating system executed by the information processing apparatus is alive, and

issuing instructions in response to detecting that the operating system is alive after the issuing of the request for active exchange, the instructions including a deletion instruction and an addition instruction, the deletion instruction being configured to execute active deletion processing of the error component, the addition instruction being configured to execute active addition processing of the other component; and

executing an active exchange processing that includes

initiating the active deletion processing in response to the deletion instruction issued from the existence monitoring processing, and

initiating the active addition processing in response to the active addition instruction issued from the existence monitoring processing.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL COVER SHEET BY REMOVING PATENT NUMBER 10586039 PREVIOUSLY RECORDED ON REEL 69272 FRAME 546. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2025
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 070764/0091 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2024
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 069272/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2020
From: TAKEUCHI, TAMOTSU
To: FUJITSU LIMITED
Reel/Frame 053253/0501 →
Priority Claims (1)
JP JP2019-138029 · Jul 26, 2019 · national
Continuity (1)
Related Publication 20210026726A1 · Jan 28, 2021