SEMICONDUCTOR WAFER THINNED BY STEALTH LASING
A semiconductor wafer thinned by a stealth lasing process, and semiconductor dies formed therefrom. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by focusing a laser at discrete points in the wafer substrate beneath the surface of the wafer. Upon completion of stealth lasing in one or more planar layers in the substrate, a portion of the substrate may be removed, leaving the wafer thinned to a desired final thickness.
1 . A semiconductor die, comprising:
a first major surface;
a plurality of integrated circuits formed in the first major surface of the wafer;
a lased, second major surface opposed to the first major surface; and
a die attach film (DAF) layer covering the lased, second major surface.
2 . The semiconductor die of claim 1 , wherein the lased, second major surface comprises a first portion of a semiconductor die substrate that was severed from a second portion of the semiconductor die substrate by a stealth lasing process.
3 . The semiconductor die of claim 1 , wherein the lased, second major surface is formed by application of a laser focused in between surfaces of a wafer from which the semiconductor die is formed.
4 . The semiconductor die of claim 1 , wherein the lased, second major surface is formed by application of a laser focused in a pattern of discrete points at one or more planar layers of the semiconductor die.
5 . The semiconductor die of claim 4 , wherein the one or more planar layers comprise four planar layers.
6 . The semiconductor die of claim 1 , wherein the lased, second major surface is also polished.
7 . The semiconductor die of claim 1 , wherein the semiconductor die has a thickness between the first and second major surfaces of between 25 microns and 36 microns.
8 . The semiconductor die of claim 1 , wherein the semiconductor die is a flash memory semiconductor die.
9 . The semiconductor die of claim 1 , wherein the DAF layer has been removed, thereby exposing the second major surface.
10 . A semiconductor wafer, comprising:
a first major surface;
a plurality of semiconductor dies, the plurality of semiconductor dies comprising integrated circuits formed in the first major surface of the wafer; and
a lased, second major surface opposed to the first major surface.
11 . The semiconductor wafer of claim 10 , wherein the lased, second major surface comprises a first portion of a semiconductor wafer substrate that was severed from a second portion of the semiconductor wafer substrate by a stealth lasing process.
12 . The semiconductor wafer of claim 10 , wherein the lased, second major surface is formed by application of a laser beam from a laser, focused in between surfaces of the wafer.
13 . The semiconductor wafer of claim 12 , wherein the laser is cycled off and on to a peak power density at a predetermined frequency as the laser beam is moved relative to the semiconductor wafer.
14 . The semiconductor wafer of claim 13 , wherein voids in the wafer are created at and around a focal point of the laser beam when the laser is cycled at its peak power density.
15 . The semiconductor wafer of claim 14 , wherein a height and width of a void of the voids is controlled by a predetermined laser beam width and a predetermined power intensity of the laser.
16 . The semiconductor wafer of claim 14 , wherein the laser beam is defocused and does not modify the wafer at predetermined distances above and below the focal point of the laser beam.
17 . The semiconductor wafer of claim 14 , wherein the voids are formed in a pattern defining one or more planar layers within the wafer, the one or more planar layers of voids defining a modified zone in the wafer allowing separation of the wafer substrate above and below the modified zone.
18 . The semiconductor wafer of claim 17 , wherein a density of the voids in a planar layer of the one or more planar layers of voids is controlled by a predetermined peak intensity cycle time of the laser and a predetermined rate of movement of the laser beam across the semiconductor wafer.
19 . The semiconductor wafer of claim 10 , wherein the lased, second major surface is also polished.
20 . A semiconductor wafer, comprising:
a first major surface;
a plurality of semiconductor dies, the plurality of semiconductor dies comprising integrated circuits formed in the first major surface of the wafer;
a second major surface opposed to the first major surface;
wherein the second major surface is defined by means for severing a first portion of the wafer from a second portion of the wafer.