IP Library Patent Application 16934247
Patent Application
App. No. 16/934,247

PERFORMANCE OPTIMIZATION OF CLOSE CODE

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Quick Facts
Patent No.
US None
App. No.
16/934,247
Abstract

Methods and systems described herein utilize a jump table in directly-addressable, near code, to facilitate improved execution of frequent calls to executable code from other workloads outside of the near code. By executing a directly-addressable call and jump instruction to access frequently-accessed executable code, indirect call instructions are avoided.

Claims (46)

1 . A method comprising:

instantiating executable code in a memory of a computing system, the executable code having a starting location in the memory;

implementing, within a near code area within the memory relative to the executable code, a jump table at a memory location proximate to a boundary of directly-addressable memory in the near code, the jump table including a plurality of entries each associated with one of a plurality of functions included in the executable code;

upon executing a call to one of the plurality of functions in the executable code from a workload:

executing a call instruction into the jump table from the workload, the call instruction including a direct address to a location in the jump table; and

executing the direct jump instruction from the jump table into the function.

2 . The method of claim 1 , wherein the executable code is directly executable by a processor of the computing system having a native instruction set architecture, and wherein the plurality of functions correspond to non-native instructions, and wherein the executable code comprises an instruction emulator configured to execute native instructions corresponding to each of the non-native instructions.

3 . The method of claim 1 , wherein the near code area comprises a memory location within an address distance of the executable code accessible via a directly-addressable call instruction in the instruction set architecture of the computing system.

4 . The method of claim 1 , further comprising:

sampling an executing workload on the computing system, the workload including calls to the plurality of functions;

determining a priority of the plurality of functions based at least in part on frequency of execution of the plurality of functions based on the sampling; and

reordering the jump table to prioritize frequently-used functions of the plurality of functions.

5 . The method of claim 4 , wherein reordering the jump table comprises ordering entries associated with the plurality of functions, at least in part, in descending order based on frequency of execution.

6 . The method of claim 1 , further comprising grouping entries in the jump table based on similarity of the functions associated with the entries.

7 . The method of claim 1 , wherein a processor of the computing system executes the call instruction and the direct jump instruction without experiencing a stall.

8 . The method of claim 1 , wherein the memory has an addressable size that is greater than an addressable range of the call instruction.

9 . The method of claim 1 , wherein the call instruction and the direct jump instruction are both unconditional instructions.

10 . The method of claim 1 , wherein the call instruction includes a 32-bit direct address.

11 . A method of executing a hosted workload executable according to a non-native instruction set architecture on a computing system having a memory and a processor implemented using a native instruction set architecture, the method comprising:

instantiating a core emulation executable at a location in memory of the computing system, the core emulation executable including a plurality of functions;

placing a jump table in memory at a location from which the core emulation executable may be reached via a direct jump instruction in the native instruction set architecture, each of a plurality of entries in the jump table including a direct jump instruction to a different one of the plurality of functions;

executing a hosted workload from the memory of the computing system, the hosted workload being located, at least in part, in code outside of a region in memory from which the core emulation executable may be reached via a direct call instruction;

upon executing a call from the workload to a function included in the plurality of functions of the core emulation executable:

performing a directly-addressable call instruction to access the jump table; and

performing a direct jump instruction from the jump table to the function within the core emulation executable.

12 . The method of claim 11 , wherein the hosted workload comprises a compiled executable that includes a plurality of calls to the core emulation executable to perform emulated versions of non-native instructions.

13 . The method of claim 11 , further comprising:

analyzing the hosted workload to identify a plurality of functions called by the hosted workload; and

grouping entries associated with at least some of the plurality of functions within the jump table based on similarity.

14 . The method of claim 11 , further comprising:

sampling execution of the hosted workload to determine frequency of execution of each of the plurality of functions; and

ordering entries in the jump table at least in part based on frequency of execution of the plurality of functions corresponding to the entries.

15 . The method of claim 11 , wherein the direct jump instruction has an addressable range that is smaller than a distance between a core function at the address of the direct jump instruction and a portion of the hosted workload from which the direct jump instruction is called.

16 . The method of claim 11 , wherein the directly-addressable call instruction includes a 32-bit direct address.

17 . The method of claim 11 , wherein a processor of the computing system executes the call instruction and the direct jump instruction without experiencing a stall.

18 . A computing system comprising:

a processor capable of executing instructions according to a native instruction set architecture;

a memory communicatively connected to the processor, the memory storing instructions which, when executed by the processor, cause the computing system to perform:

instantiating a core emulation executable at a location in memory of the computing system, the core emulation executable including a plurality of functions;

placing a jump table in memory at a location from which the core emulation executable may be reached via a direct jump instruction in the native instruction set architecture, each of a plurality of entries in the jump table including a direct jump instruction to a different one of the plurality of functions;

executing a hosted workload from the memory of the computing system, the hosted workload located at least in part in code outside of a region in memory from which the core emulation executable may be reached via a direct call instruction; and

upon executing a call from the workload to a function included in the plurality of functions of the core emulation executable:

performing a directly-addressable call instruction to access the jump table; and

performing a direct jump instruction from the jump table to the function within the core emulation executable.

19 . The computing system of claim 18 , wherein the computing system is implemented using an x86-based instruction set architecture.

20 . The computing system of claim 19 , wherein the hosted workload is implemented using a non-native instruction set architecture different from the native instruction set architecture.

Assignments (3)
SECURITY INTEREST Recorded Jun 14, 2021
From: UNISYS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056531/0150 →
SECURITY INTEREST Recorded Nov 19, 2020
From: UNISYS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 054481/0865 →
SECURITY INTEREST Recorded Oct 30, 2020
From: UNISYS CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 054226/0638 →