IP Library Granted Patent US 11,195,582
Granted Patent B2
US 11,195,582 · App. 16/935,503 · Granted Dec 7, 2021

Non-volatile memory device and method of writing to non-volatile memory device

Inventors: Yuhei Yoshimoto (Hyogo, JP); Yoshikazu Katoh (Osaka, JP); Naoto Kii (Osaka, JP)
Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
G11C13/0059G11C13/004G11C13/0007G11C13/0069G11C2213/79
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,195,582
App. No.
16/935,503
Granted
Dec 7, 2021
Kind
B2
Abstract

A non-volatile memory device includes: a memory group of a plurality of variable resistance memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other; and a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells included in the memory group. Dummy data, for reducing a correlation between a side-channel leakage generated when the read operation is performed by the read circuit and information data recorded in the at least one data cell, is recorded in the at least one dummy cell.

Claims (29)

1. A non-volatile memory device, comprising:

a memory group of a plurality of memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other, the plurality of memory cells being variable resistance memory cells;

a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells included in the memory group,

wherein dummy data is recorded in the at least one dummy cell, the dummy data being for reducing a correlation between a side-channel leakage and information data recorded in the at least one data cell, the side-channel leakage being generated when the read operation is performed by the read circuit.

2. The non-volatile memory device according to claim 1 , further comprising:

a write circuit which performs a write operation for writing the dummy data on the at least one dummy cell, based on the information data recorded in the at least one data cell.

3. The non-volatile memory device according to claim 1 ,

wherein physically unclonable function (PUF) data is recorded in the plurality of memory cells, the PUF data being device-specific data in which variations in physical characteristics are used.

4. The non-volatile memory device according to claim 3 ,

wherein the plurality of memory cells include a plurality of variable memory cells each of which is a memory cell in a variable state where a resistance value reversibly changes between a plurality of variable resistance value ranges in response to an application of a plurality of electric signals which are mutually different, and

resistance value variations of the plurality of variable memory cells in a same resistance state are used as the variations in physical characteristics used in the PUF data.

5. The non-volatile memory device according to claim 3 ,

wherein the plurality of memory cells include:

a variable memory cell which is a memory cell in a variable state where a resistance value reversibly changes between a plurality of variable resistance value ranges in response to an application of a plurality of electric signals which are mutually different; and

a memory cell in an initial state where the memory cell does not change to the variable state unless a forming stress is applied, the initial state being in an initial resistance range in which a resistance value does not overlap any of the plurality of variable resistance value ranges, the forming stress being an electric stress which changes the memory cell to the variable state,

wherein variations in a cumulative pulse time period necessary for the forming stress are used as the variations in physical characteristics used in the PUF data.

6. The non-volatile memory device according to claim 3 ,

wherein the PUF data is recorded in the at least one data cell, and

error correction data of the PUF data is not recorded in the plurality of memory cells included in the memory group.

7. The non-volatile memory device according to claim 1 ,

wherein the dummy data is data for setting a Hamming weight of the at least one data cell and the at least one dummy cell to a predetermined value.

8. The non-volatile memory device according to claim 1 ,

wherein the dummy data is random number data.

9. The non-volatile memory device according to claim 6 ,

wherein the plurality of memory cells include a variable memory cell which is a memory cell in a variable state where a resistance value reversibly changes between a plurality of variable resistance value ranges in response to an application of a plurality of electric signals which are mutually different,

the at least one dummy cell is the variable memory cell, and

the dummy data is a resistance value in a same resistance state.

10. A method of writing to a non-volatile memory device including: a memory group of a plurality of memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other, the plurality of memory cells being variable resistance memory cells; and a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells, the method comprising:

writing dummy data to the at least one dummy cell, the dummy data being for reducing a correlation between a side-channel leakage and information data recorded in the at least one data cell, the side-channel leakage being generated when the read operation is performed by the read circuit.

Assignments (2)
CHANGE OF NAME Recorded May 14, 2021
From: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 056245/0395 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2020
From: YOSHIMOTO, YUHEI; KATOH, YOSHIKAZU; KII, NAOTO
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 053544/0528 →