IP Library Granted Patent US 10,957,710
Granted Patent B2
US 10,957,710 · App. 16/936,561 · Granted Mar 23, 2021

Three dimensional semiconductor memory including pillars having joint portions between columnar sections

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,957,710
App. No.
16/936,561
Granted
Mar 23, 2021
Kind
B2
Abstract

According to one embodiment, a semiconductor memory includes a plurality of conductors stacked with insulators being interposed therebetween and a pillar through the plurality of conductors. The pillar includes a first columnar section, a second columnar section, and a joint portion between the first columnar section and the second columnar section. The pillar comprises portions that cross the respective conductors and that each function as part of a transistor. The plurality of conductors include a first conductor. The first conductor is closest to the joint portion among the plurality of conductors through the second columnar section, and includes a bending portion formed along the joint portion.

Claims (32)

1. A semiconductor memory comprising:

a plurality of conductors stacked in a first direction with insulators being interposed therebetween; and

a pillar extending in the first direction through the plurality of conductors, the pillar including a first columnar section, a second columnar section above the first columnar section, and a joint portion between the first columnar section and the second columnar section, and the pillar comprising portions that cross the respective conductors, the portions respectively functioning as part of a transistor,

wherein the plurality of conductors include a first conductor that is closest to the joint portion among the plurality of conductors through the second columnar section, the first conductor includes a first portion surrounding the pillar, a second portion surrounding the first portion, and a third portion surrounding the second portion when viewed from the first direction, a bottom surface of the second portion has the same level in the first direction as a bottom surface of the third portion, and a bottom surface of the first portion is upper than the bottom surfaces of the second and third portions.

2. The memory of claim 1 , wherein the joint portion abuts each of the first columnar section and the second columnar section.

3. The memory of claim 2 , wherein an outer diameter of the joint portion in a cross-section area parallel to a surface of a substrate, is larger than an outer diameter of the second columnar section in a cross-section area parallel to the surface of the substrate and including a boundary portion between the second columnar section and the joint portion.

4. The memory of claim 3 , wherein the outer diameter of the joint portion is larger than an outer diameter of the first columnar section in a cross-section area parallel to the substrate and including a boundary portion between the first columnar section and the joint portion.

5. The memory of claim 3 , wherein a distance, in the first direction between the bottom surface of the first portion and the bottom surface of the third portion is smaller than a thickness of the first conductor in the first direction.

6. The memory of claim 5 , wherein the distance is equal to or smaller than a half of the thickness.

7. The memory of claim 1 , wherein the plurality of conductors include a second conductor that is second closest to the joint portion among the plurality of conductors through the second columnar section, and the second conductor includes a portion bending indirectly along the joint portion.

8. The memory of claim 1 , wherein a transistor provided in a portion where the first conductor crosses the second columnar section is not used for storing data.

9. The memory of claim 1 , wherein the plurality of conductors include a third conductor that is closest to the joint portion among the plurality of conductors through the first columnar section,

a first distance is smaller than a second distance,

the first distance is a distance, in a stacking direction of the plurality of conductors, between adjacent conductors among the plurality of conductors through the second columnar section, and

the second distance is a distance in the stacking direction between the first conductor and the third conductor.

10. The memory of claim 9 , wherein the third conductor has no portion bending along the joint portion.

11. The memory of claim 9 , wherein a transistor provided in a portion where the third conductor crosses the first columnar section is not used for storing data.

12. A semiconductor memory comprising:

a plurality of conductors stacked in a first direction with insulators being interposed therebetween; and

a pillar extending in the first direction through the plurality of conductors, the pillar including a first columnar section and a second columnar section on the first columnar section, and the pillar comprising portions that cross the respective conductors, the portions respectively functioning as part of a transistor,

wherein the plurality of conductors include a first conductor that is closest to the first columnar section among the plurality of conductors through the second columnar section, the first conductor includes a first portion surrounding the pillar, a second portion surrounding the first portion, and a third portion surrounding the second portion when viewed from the first direction, a bottom surface of the second portion has the same level in the first direction as a bottom surface of the third portion, and a bottom surface of the first portion is upper than the bottom surfaces of the second and third portions.

13. The memory of claim 12 , wherein, in a boundary portion between the first columnar section and the second columnar section, an outer diameter of the first columnar section in a cross-section area parallel to a surface of a substrate is larger than an outer diameter of the second columnar section in a cross-section area parallel to the surface of the substrate.

14. The memory of claim 13 , wherein a distance, in the first direction between the bottom surface of the first portion and the bottom surface of the third portion is smaller than a thickness of the first conductor in the first direction.

15. The memory of claim 14 , wherein the distance is equal to or smaller than a half of the thickness.

16. The memory of claim 12 , wherein the plurality of conductors include a second conductor that is second closest to the first columnar section among the plurality of conductors through the second columnar section, and the second conductor includes a portion bending indirectly along the first columnar section.

17. The memory of claim 12 , wherein a transistor provided in a portion where the first conductor crosses the second columnar section is not used for storing data.

18. The memory of claim 12 , wherein the plurality of conductors include a third conductor that is closest to the second columnar section among the plurality of conductors through the first columnar section,

a first distance is smaller than a second distance,

the first distance is a distance, in a stacking direction of the plurality of conductors, between adjacent conductors among the plurality of conductors through the second columnar section,

the second distance is a distance in the stacking direction between the first conductor and the third conductor.

19. The memory of claim 18 , wherein the third conductor has no portion bending along the joint portion.

20. The memory of claim 18 , wherein a transistor provided in a portion where the third conductor crosses the first columnar section is not used for storing data.

Assignments (1)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →