IP Library Granted Patent US 11,500,717
Granted Patent B2
US 11,500,717 · App. 16/936,709 · Granted Nov 15, 2022

Method for detecting data storage system, device and data storage system

Inventors: Min Zhang (Shanghai, CN); Zhonghua Zhu (Shanghai, CN); Guifeng Tang (Shanghai, CN); Qiulin Cheng (Shanghai, CN); Yechen Huang (Shanghai, CN); Zhenhua Dong (Shanghai, CN); Thomas Dibb (Rutland, MA)
Assignee: EMC IP Holding Company LLC
G06F11/0793G06F11/0727G06F11/0751G06F11/0772G06F13/4022G06F13/4282G06F2213/0026
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,500,717
App. No.
16/936,709
Granted
Nov 15, 2022
Kind
B2
Abstract

Techniques involve: acquiring, through a first downstream port of a first switch of a data storage system, information indicating an error of a storage device array from a second switch of the data storage system, wherein the first switch and the second switch are connected to the storage device array and the first downstream port is connected to a second downstream port of the second switch; executing, based on the acquired information, actual actions intended for solving the error; and in response to the executed actual actions failing to match with expected actions for the error, issuing an alarm indicating failure of processing the error.

Claims (61)

1. A method for detecting a data storage system, comprising:

acquiring, through a first downstream port of a first switch of the data storage system, information indicating an error of a storage device array from a second switch of the data storage system, wherein the first switch and the second switch are connected to the storage device array and the first downstream port is connected to a second downstream port of the second switch;

executing, based on the acquired information, actual actions intended for solving the error; and

in response to the executed actual actions failing to match with expected actions for the error, issuing an alarm indicating failure of processing the error.

2. The method of claim 1 , wherein the acquired information indicating the error of the storage device array is inputted at the second downstream port of the second switch and transmitted to the first switch via the first downstream port.

3. The method of claim 1 , wherein each switch is a PCIe (Peripheral Component Interconnect Express) switch.

4. The method of claim 1 , further comprising:

performing a set of data storage operations which stores data into and retrieves data from the storage device array on behalf of a set of external devices while concurrently acquiring, executing, and issuing.

5. A data storage system, comprising:

a first switch including a first downstream port;

a second switch including a second downstream port connected to the first downstream port;

a first processor connected to the first switch via an upstream port of the first switch;

a second processor connected to the second switch via an upstream port of the second switch; and

a storage device array to which both the first switch and the second switch are connected;

wherein the first switch is configured to acquire, through the first downstream port, information indicating an error of the storage device array inserted at the second downstream port; and

wherein the first switch is configured to execute a method which includes:

acquiring, through the first downstream port of the first switch of the data storage system, the information indicating the error of the storage device array from the second switch of the data storage system;

executing, based on the acquired information, actual actions intended for solving the error; and

in response to the executed actual actions failing to match with expected actions for the error, issuing an alarm indicating failure of processing the error.

6. The data storage system of claim 5 , wherein

the first downstream port of the first switch is configured to connect the second downstream port of the second switch;

a third downstream port of the first switch is configured to connect a fourth downstream port of the second switch;

a first downstream port group of the first switch is configured to send, via an upstream port of the first switch, information from connected storage devices to the first processor;

a second downstream port group of the first switch is configured to send, via the third downstream port and the fourth downstream port, information from connected storage devices to the second processor;

a third downstream port group of the second switch is configured to send, via an upstream port of the second switch, information from connected storage devices to the second processor;

a fourth downstream port group of the second switch is configured to send, via the first downstream port and the second downstream port, information from a connected storage device to the first processor.

7. The data storage system of claim 6 ,

wherein the first switch comprises:

a first upstream port configured to connect the first downstream port group; and

a second upstream port configured to connect, via the first downstream port and the second downstream port, the fourth downstream port group;

wherein the second switch comprises:

a third upstream port configured to connect the third downstream port group; and

a fourth upstream port configured to connect, via the third downstream port and the fourth downstream port, the second downstream port group.

8. The data storage system of claim 7 , wherein the first downstream port group, the second downstream port group, the third downstream port group and the fourth downstream port group are configured to have the same number of downstream ports.

9. The data storage system of claim 5 , wherein the acquired information indicating the error of the storage device array is inputted at the second downstream port of the second switch and transmitted to the first switch via the first downstream port.

10. The data storage system of claim 5 , wherein each switch is a PCIe (Peripheral Component Interconnect Express) switch.

11. The data storage system of claim 5 wherein the method further includes:

performing a set of data storage operations which stores data into and retrieves data from the storage device array on behalf of a set of external devices while concurrently acquiring, executing, and issuing.

12. An electronic device, comprising:

a processor and a first switch which are operative to form at least part of a data storage system, wherein the processor is constructed and arranged to:

acquire, through a first downstream port of the first switch of the data storage system, information indicating an error of a storage device array from a second switch of the data storage system, wherein the first switch and the second switch are connected to the storage device array and the first downstream port is connected to a second downstream port of the second switch,

execute, based on the acquired information, actual actions intended for solving the error, and

in response to the executed actual actions failing to match with expected actions for the error, issue an alarm indicating failure of processing the error.

13. The electronic device of claim 12 , wherein the acquired information indicating the error of the storage device array is inputted at the second downstream port of the second switch and transmitted to the first switch via the first downstream port.

14. The electronic device of claim 12 , wherein the first switch and the second switch are PCIe (Peripheral Component Interconnect Express) switches.

15. The electronic device of claim 12 , wherein the processor is further constructed and arranged to:

perform a set of data storage operations which stores data into and retrieves data from the storage device array on behalf of a set of external devices while concurrently acquiring the information indicating the error, executing the actual actions, and issuing the alarm.

16. The electronic device of claim 12 , wherein

the first downstream port of the first switch is configured to connect the second downstream port of the second switch;

a third downstream port of the first switch is configured to connect a fourth downstream port of the second switch;

a first downstream port group of the first switch is configured to send, via an upstream port of the first switch, information from connected storage devices to the first processor;

a second downstream port group of the first switch is configured to send, via the third downstream port and the fourth downstream port, information from connected storage devices to the second processor;

a third downstream port group of the second switch is configured to send, via an upstream port of the second switch, information from connected storage devices to the second processor;

a fourth downstream port group of the second switch is configured to send, via the first downstream port and the second downstream port, information from a connected storage device to the first processor.

17. The electronic device of claim 12 , wherein the first switch comprises:

a first upstream port configured to connect the first downstream port group; and

a second upstream port configured to connect, via the first downstream port and the second downstream port, the fourth downstream port group;

wherein the second switch comprises:

a third upstream port configured to connect the third downstream port group; and

a fourth upstream port configured to connect, via the third downstream port and the fourth downstream port, the second downstream port group.

18. The electronic device of claim 12 , wherein the first downstream port group, the second downstream port group, the third downstream port group and the fourth downstream port group are configured to have the same number of downstream ports.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053578/0183) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060332/0864 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053574/0221) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060333/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053573/0535) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060333/0106 →
RELEASE OF SECURITY INTEREST AT REEL 053531 FRAME 0108 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0371 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053578/0183 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2020
From: ZHANG, MIN; ZHU, ZHONGHUA; TANG, GUIFENG; CHENG, QIULIN; HUANG, YECHEN; DONG, ZHENHUA; DIBB, THOMAS
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 053562/0300 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053573/0535 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053574/0221 →
SECURITY AGREEMENT Recorded Aug 18, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 053531/0108 →