IP Library Granted Patent US 11,294,692
Granted Patent B2
US 11,294,692 · App. 16/940,098 · Granted Apr 5, 2022

Basic input output system (BIOS)—identified memory size and node address range mirroring system

Inventors: Ching-Lung Chao (Austin, TX); Shih-Hao Wang (Taipei, TW)
Assignee: Dell Products L.P.
G06F9/4406G06F9/30189G06F9/4411G06F12/0238G06F2212/2542G11C16/10G11C16/32H01L25/0657
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Quick Facts
Patent No.
US 11,294,692
App. No.
16/940,098
Granted
Apr 5, 2022
Kind
B2
Abstract

An address range mirroring system includes a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem, an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes, and a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes. The BIOS identifies an address range mirroring memory size that was provided by the operating system, and an address range mirroring node usage identification that was provided by the operating system. The BIOS then configures address range mirroring according to the address range mirroring memory size in the respective memory subsystem in each of a subset of the plurality of processing subsystem/memory subsystem nodes, with the subset of the plurality of processing subsystem/memory subsystem nodes based on the address range mirroring node usage identification.

Claims (44)

1. An address range mirroring system, comprising:

a plurality of processing subsystem/memory subsystem nodes, wherein each of the plurality of processing subsystem/memory subsystem nodes include a respective processing subsystem coupled to a respective memory subsystem;

an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes; and

a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes, wherein the BIOS is configured to:

identify an address range mirroring memory size that was provided by the operating system;

identify an address range mirroring node usage identification that was provided by the operating system and that identifies a subset of the plurality of processing subsystem/memory subsystem nodes for which to configure address range mirroring; and

configure, in the respective memory subsystem in each of the subset of the plurality of processing subsystem/memory subsystem nodes identified by the address range mirroring node usage identification, address range mirroring according to the address range mirroring memory size.

2. The system of claim 1 , wherein the BIOS includes:

an address range mirroring variable structure including:

an address range mirroring memory size request field that is configured to store address range mirroring memory size that was provided by the operating system; and

at least one address range mirroring node usage identification field that is configured to store the address range mirroring node usage identification that was provided by the operating system.

3. The system of claim 1 , wherein the address range mirroring node usage identification is provided by an address range mirroring node usage flag that prevents the BIOS from configuring address range mirroring in all of the plurality of processing subsystem/memory subsystem nodes.

4. The system of claim 1 , wherein the address range mirroring node usage identification is provided by an address range mirroring node usage flag that causes the BIOS to configure address range mirroring according to the address range mirroring memory size in the memory subsystem in one of the plurality of processing subsystem/memory subsystem nodes.

5. The system of claim 1 , wherein the address range mirroring node usage identification is provided by an address range mirroring node usage flag that causes the BIOS to configure address range mirroring according to the address range mirroring memory size in the respective memory subsystem in more than one of the plurality of processing subsystem/memory subsystem nodes but less than all of the plurality of processing subsystem/memory subsystem nodes.

6. The system of claim 1 , wherein the plurality of processing subsystem/memory subsystem nodes are provided by Non-Uniform Memory Access (NUMA) nodes.

7. The system of claim 1 , wherein the respective processing system in at least one of the plurality of processing subsystem/memory subsystem nodes is configured to:

mirror, based on the configuration of address range mirroring in each of the subset of the plurality of processing subsystem/memory subsystem nodes, data stored by operating system in the respective memory subsystem in each of the subset of the plurality of processing subsystem/memory subsystem nodes.

8. An Information Handling System (IHS), comprising:

a Basic Input/Output (BIOS) processing system; and

a BIOS memory system that is coupled to the BIOS processing system and that includes instructions that, when executed by the BIOS processing system, cause the BIOS processing system to provide a BIOS engine that is configured to:

identify an address range mirroring memory size that was received from an operating system provided by at least one of a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem;

identify an address range mirroring node usage identification that was received from the operating system and that identifies a subset of the plurality of processing subsystem/memory subsystem nodes for which to configure address range mirroring; and

configure, in the respective memory subsystem in each of the subset of the plurality of processing subsystem/memory subsystem nodes identified by the address range mirroring node usage identification, address range mirroring according to the address range mirroring memory size.

9. The IHS of claim 8 , further comprising:

an address range mirroring variable structure including:

an address range mirroring memory size request field that is configured to store address range mirroring memory size that was received by the operating system; and

at least one address range mirroring node usage identification field that is configured to store the address range mirroring node usage identification that was received by the operating system.

10. The IHS of claim 8 , wherein the address range mirroring node usage identification is provided by an address range mirroring node usage flag that prevents the BIOS engine from configuring address range mirroring in all of the plurality of processing subsystem/memory subsystem nodes.

11. The IHS of claim 8 , wherein the address range mirroring node usage identification is provided by an address range mirroring node usage flag that causes the BIOS engine to configure address range mirroring according to the address range mirroring memory size in the memory subsystem in one of the plurality of processing subsystem/memory subsystem nodes.

12. The IHS of claim 8 , wherein the address range mirroring node usage identification is provided by an address range mirroring node usage flag that causes the BIOS engine to configure address range mirroring according to the address range mirroring memory size in the respective memory subsystem in more than one of the plurality of processing subsystem/memory subsystem nodes but less than all of the plurality of processing subsystem/memory subsystem nodes.

13. The IHS of claim 8 , wherein the plurality of processing subsystem/memory subsystem nodes are provided by Non-Uniform Memory Access (NUMA) nodes.

14. A method for performing address range mirroring, comprising:

identifying, by a Basic Input/Output System (BIOS), an address range mirroring memory size that was received from an operating system provided by at least one of a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem;

identifying, by the BIOS, an address range mirroring node usage identification that was received from the operating system and that identifies a subset of the plurality of processing subsystem/memory subsystem nodes for which to configure address range mirroring; and

configuring, by the BIOS in each of the subset of the plurality of processing subsystem/memory subsystem nodes identified by the address range mirroring node usage identification, address range mirroring according to the address range mirroring memory size.

15. The method of claim 14 , further comprising:

retrieving, by the BIOS from an address range mirroring memory size request field included in an address range mirroring variable structure, the address range mirroring memory size that was received by the operating system; and

retrieving, by the BIOS from at least one address range mirroring node usage identification field included in the address range mirroring variable structure, the address range mirroring node usage identification that was received by the operating system.

16. The method of claim 14 , wherein the address range mirroring node usage identification is provided by an address range mirroring node usage flag that prevents the BIOS from configuring address range mirroring in all of the plurality of processing subsystem/memory subsystem nodes.

17. The method of claim 14 , wherein the address range mirroring node usage identification is provided by an address range mirroring node usage flag that causes the BIOS to configure address range mirroring according to the address range mirroring memory size in the memory subsystem in one of the plurality of processing subsystem/memory subsystem nodes.

18. The method of claim 14 , wherein the address range mirroring node usage identification is provided by an address range mirroring node usage flag that causes the BIOS to configure address range mirroring according to the address range mirroring memory size in the respective memory subsystem in more than one of the plurality of processing subsystem/memory subsystem nodes but less than all of the plurality of processing subsystem/memory subsystem nodes.

19. The method of claim 14 , wherein the plurality of processing subsystem/memory subsystem nodes are provided by Non-Uniform Memory Access (NUMA) nodes.

20. The method of claim 14 , further comprising:

mirroring, by the respective processing system in at least one of the plurality of processing subsystem/memory subsystem nodes based on the configuration of address range mirroring in each of the subset of the plurality of processing subsystem/memory subsystem nodes, data stored by operating system in the respective memory subsystem in each of the subset of the plurality of processing subsystem/memory subsystem nodes.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053574/0221) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060333/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053578/0183) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060332/0864 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053573/0535) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060333/0106 →
RELEASE OF SECURITY INTEREST AT REEL 053531 FRAME 0108 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0371 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053578/0183 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053573/0535 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053574/0221 →
SECURITY AGREEMENT Recorded Aug 18, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 053531/0108 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2020
From: CHAO, CHING-LUNG; WANG, SHIH-HAO
To: DELL PRODUCTS L.P.
Reel/Frame 053322/0099 →