Solar array system and method of manufacturing
A space-grade solar array includes relatively small cells with integrated wiring embedded into or incorporated directly onto a printed circuit board. The integrated wiring provides an interface for solar cells having back side electrical contacts. The single side contacts enable the use of pick and place (PnP) technology in manufacturing the space-grade solar array. The solar cell is easily and efficiently packaged and electrically interconnected with other solar cells on a solar panel such as by using PnP process. The back side contacts are matched from a size and positioning standpoint to corresponding contacts on the printed circuit board.
1. A method of manufacturing a space-grade solar array, comprising:
providing a multi-junction solar cell wafer having a plurality of solar cells, wherein each solar cell already has a positive electrical contact and a negative electrical contact both located on a common, back side of the solar cell;
covering the multi-junction solar cell wafer with a protective coverglass, wherein the protective coverglass is a space-grade, radiation-protective coverglass;
bonding the protective coverglass to the multi-junction solar cell wafer;
cutting both the multi-junction solar cell wafer and the protective coverglass into a plurality of diced solar cells while the protective coverglass is positioned on the multi-junction solar cell wafer; and
using a pick-and-place robot to position the diced solar cells onto a printed circuit board with the back side of each diced solar cell in contact with a front side of the printed circuit board such that the positive electrical contact and the negative electrical contact of each diced solar cell electrically couples to a corresponding electrical contact of the printed circuit board, and wherein the printed circuit board has electrical traces that include solar cell-to-solar cell interconnect wiring and bypass and blocking diodes, and wherein the positive electrical contact and the negative electrical contact of each diced solar cell has a coefficient of thermal expansion that matches a coefficient of thermal expansion of the electrical contact of the printed circuit board.
2. The method of claim 1 , wherein the printed circuit board is rigid.
3. The method of claim 1 , wherein the printed circuit board is flexible.
4. The method of claim 1 , wherein the printed circuit board serves as a solar array panel.
5. The method of claim 1 , further comprising positioning the printed circuit board with the solar cells onto a solar array panel.
6. The method of claim 1 , wherein the solar cell wafer is cut into solar cells that are no larger than 20 cm 2 .
7. The method of claim 1 , further comprising locating the bypass and blocking diodes onto a back side of the printed circuit board.
8. The method of claim 1 , further comprising using the pick-and-place robot to position the solar cells onto the printed circuit board.
9. The method of claim 1 , wherein the pick-and-place robot is used automatically to position the solar cells onto the printed circuit board without human intervention.
10. The method of claim 1 , wherein both the positive electrical contact and the negative electrical contact are exposed contacts.
11. The method of claim 1 , further comprising removing and replacing only a single solar cell from the printed circuit board.
12. The method of claim 11 , further comprising removing and replacing a single solar cell from the printed circuit board without affecting a power capability of the entire solar array.
13. The method of claim 12 , further comprising placing only bypass and blocking diodes on a back side of the printed circuit board.
14. The method of claim 1 , wherein the positive electrical contact and the negative electrical contact of each diced solar cell has a size that matches a size of respective electrical contact of the printed circuit board.
15. The method of claim 1 , wherein only the diced solar cells are positioned on the printed circuit board.