IP Library Granted Patent US 12,271,752
Granted Patent B2
US 12,271,752 · App. 16/945,387 · Granted Apr 8, 2025

Techniques for managing cores for storage

Inventors: John Gillono (North Chelmsford, MA); Philippe Armangau (Acton, MA); Vamsi K. Vankamamidi (Hopkinton, MA); Ashok Tamilarasan (Shrewsbury, MA)
Assignee: EMC IP Holding Company LLC
G06F9/4881G06F3/0611G06F3/0653G06F3/0659G06F3/067G06F9/30047G06F9/5027G06F2209/5018
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Quick Facts
Patent No.
US 12,271,752
App. No.
16/945,387
Granted
Apr 8, 2025
Kind
B2
Abstract

A method of managing CPU cores in a data storage apparatus (DSA) configured to perform both host I/O (Input/Output) processing and background storage processing is provided. The method includes (a) selectively classifying background storage tasks in one of a first classification for longer-running tasks and a second classification for shorter-running tasks; (b) selecting CPU cores that are running fewer than a threshold number of first-classification background tasks to process host I/O requests; and (c) processing the host I/O requests on their selected CPU cores. An apparatus, system, and computer program product for performing a similar method are also provided.

Claims (48)

1. A method of managing CPU (Central Processing Unit) cores in a data storage apparatus (DSA) configured to perform both host I/O (Input/Output) processing and background storage processing, the method comprising:

prior to assigning respective background storage tasks to CPU cores, selectively classifying the respective background storage tasks in one of a first classification for longer-running tasks and a second classification for shorter-running tasks, wherein the longer-running tasks are known in advance to run for longer durations than the shorter-running tasks, the longer-running tasks including flush and high-priority RAID rebuild tasks and the shorter-running tasks including other types of tasks that are not flush or high-priority RAID rebuild tasks;

selecting CPU cores that are running fewer than a threshold number of first-classification background storage tasks to process host I/O requests, the threshold number being an integer greater than zero;

assigning second-classification background storage tasks to CPU cores based on numbers of background storage tasks running on each CPU core;

receiving a plurality of host I/O requests; and

processing the plurality of host I/O requests on the selected CPU cores,

wherein the method further comprises, for each first-classification background storage task:

selecting a CPU core within a predefined subset of the CPU cores that is running fewer than a maximum number of first-classification background storage tasks to process the respective first-classification background storage task, the predefined subset having a fixed number of CPU cores that is smaller than a total number of CPU cores available to perform the host I/O processing and background storage processing, the maximum number being an integer greater than zero; and

processing the respective first-classification background storage task on its selected CPU core within the predefined subset.

2. The method of claim 1 wherein the threshold number is one.

3. The method of claim 2 wherein the maximum number is also one.

4. The method of claim 1 wherein selectively classifying background storage tasks includes classifying flush tasks into the first classification, flush tasks being tasks that persistently store data from a cache into long-term persistent storage.

5. The method of claim 4 wherein selectively classifying background storage tasks further includes classifying rebuild tasks into the first classification, rebuild tasks being tasks that reconstruct data of a failed drive onto a replacement drive.

6. The method of claim 5 ,

wherein the maximum number is at least two; and

selecting the CPU core within the predefined subset of the CPU cores includes, for a flush task, selecting as the CPU core a CPU core from the predefined subset that is not running a rebuild task.

7. The method of claim 1 wherein the fixed number of CPU cores is within a range of 50% to 75% of the total number of CPU cores available to perform the host I/O processing and background storage processing.

8. The method of claim 7 wherein the total number of CPU cores available to perform the host I/O processing and background storage processing is smaller than a total number of CPU cores of the DSA.

9. The method of claim 1 wherein assigning second-classification background storage tasks to CPU cores based on numbers of background storage tasks running on each CPU core includes assigning second-classification background storage tasks to CPU cores having fewest background storage tasks running thereon within a group of CPU cores that is smaller than the total number of CPU cores available to perform the host I/O processing and background storage processing, up to a preferred threshold number of running background storage tasks.

10. The method of claim 9 wherein assigning second-classification background storage tasks to CPU cores based on numbers of background storage tasks running on each CPU core further includes, once the preferred threshold number of running background storage tasks has been reached on the CPU cores of the group, assigning second-classification background storage tasks to CPU cores not belonging to the group having fewest background storage tasks running thereon, up to the preferred threshold number of running background storage tasks.

11. The method of claim 10 wherein assigning second-classification background storage tasks to CPU cores based on numbers of background storage tasks running on each CPU core further includes, once the preferred threshold number of running background storage tasks has been reached on the CPU cores not belonging the group, assigning second-classification background storage tasks to CPU cores belonging to the group having fewest background storage tasks running thereon, up to an overall threshold number of running background storage tasks, the overall threshold number being larger than the preferred threshold number.

12. A data storage apparatus (DSA) comprising:

network interface circuitry connecting to a remote host over a network;

persistent storage storing data; and

a plurality of CPU (Central Processing Unit) cores connected to memory, the CPU cores connected to the memory being configured to perform both host I/O (Input/Output) processing and background storage processing and to:

prior to assignment of respective background storage tasks to CPU cores, selectively classify the respective background storage tasks in one of a first classification for longer-running tasks and a second classification for shorter-running tasks, wherein the longer-running tasks are known in advance to run for longer durations than the shorter-running tasks, the longer-running tasks including flush and high-priority RAID rebuild tasks and the shorter-running tasks including other types of tasks that are not flush or high-priority RAID rebuild tasks;

select CPU cores that are running fewer than a threshold number of first-classification background storage tasks to process host I/O requests, the threshold number being an integer greater than zero;

assign second-classification background storage tasks to CPU cores based on numbers of background storage tasks running on each CPU core;

receive a plurality of host I/O requests; and

process the plurality of host I/O requests on the selected CPU cores,

wherein the plurality of CPU cores connected to the memory is further configured to:

select a CPU core within a predefined subset of the CPU cores that is running fewer than a maximum number of first-classification background storage tasks to process the respective first-classification background storage task, the predefined subset having a fixed number of CPU cores that is smaller than a total number of CPU cores available to perform the host I/O processing and background storage processing, the maximum number being an integer greater than zero; and

process the respective first-classification background storage task on its selected CPU core within the predefined subset.

13. The DSA of claim 12 wherein the fixed number of CPU cores is within a range of 50% to 75% of the total number of CPU cores available to perform the host I/O processing and background storage processing.

14. The DSA of claim 13 wherein the total number of CPU cores available to perform the host I/O processing and background storage processing is smaller than a total number of CPU cores of the DSA.

15. A computer program product comprising a non-transitory computer-readable storage medium storing a set of instructions, which, when performed by processing circuitry of a data storage apparatus (DSA), cause the DSA to manage CPU (Central Processing Unit) cores configured to perform both host I/O (Input/Output) processing and background storage processing by:

prior to assigning respective background storage tasks to CPU cores, selectively classifying the respective background storage tasks in one of a first classification for longer-running tasks and a second classification for shorter-running tasks, wherein the longer-running tasks are known in advance to run for longer durations than the shorter-running tasks, the longer-running tasks including flush and high-priority RAID rebuild tasks and the shorter-running tasks including other types of tasks that are not flush or high-priority RAID rebuild tasks;

selecting CPU cores that are running fewer than a threshold number of first-classification background storage tasks to process host I/O requests, the threshold number being an integer greater than zero;

assigning second-classification background storage tasks to CPU cores based on numbers of background storage tasks running on each CPU core;

receiving a plurality of host I/O requests; and

processing the plurality of host I/O requests on the selected CPU cores,

wherein the set of instructions, when performed by the processing circuitry, further cause the DSA to, for each first-classification background storage task:

select a CPU core within a predefined subset of the CPU cores that is running fewer than a maximum number of first-classification background storage tasks to process the respective first-classification background storage task, the predefined subset having a fixed number of CPU cores that is smaller than a total number of CPU cores available to perform the host I/O processing and background storage processing, the maximum number being an integer greater than zero; and

process the respective first-classification background storage task on its selected CPU core within the predefined subset.

16. The computer program product of claim 15 wherein the threshold number is one.

17. The method of claim 1 , wherein the second-classification tasks include a garbage collection task.

18. The method of claim 17 , wherein the second-classification tasks further include a decrement reference count task.

19. The method of claim 1 , wherein the second-classification tasks further include a low-priority rebuild task.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053573/0535) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060333/0106 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053574/0221) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060333/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053578/0183) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060332/0864 →
RELEASE OF SECURITY INTEREST AT REEL 053531 FRAME 0108 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0371 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2020
From: GILLONO, JOHN; ARMANGAU, PHILIPPE; VANKAMAMIDI, VAMSI K; TAMILARASAN, ASHOK
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 053611/0297 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053578/0183 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053574/0221 →
SECURITY INTEREST Recorded Aug 21, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 053573/0535 →
SECURITY AGREEMENT Recorded Aug 18, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 053531/0108 →