Apparatus and methods for amplifier input-overvoltage protection with low leakage current

1. An amplifier having input-overvoltage protection with low leakage current, the amplifier comprising:

a pair of input terminals configured to receive a differential input signal, wherein the pair of input terminals includes a first input terminal and a second input terminal;

a differential pair of input transistors configured to amplify the differential input signal, wherein the differential pair of input transistors includes a first input transistor and a second input transistor connected at a tail node;

a first protection transistor in series between the first input terminal and a control input of the first input transistor;

a voltage source connected between the tail node and a control input of the first protection transistor;

a current source configured to generate a bias current, the current source including a first terminal directly connected to the tail node; and

a voltage clamp configured to provide clamping between the control input of the first input transistor and a control input of the second input transistor.

2. The amplifier of claim 1 , wherein an impedance of the first protection transistor is configured to increase in response to an excursion of the first or second input terminal.

3. The amplifier of claim 1 , further comprising a second protection transistor in series between the second input terminal and the control input of the second input transistor, wherein the voltage clamp is bidirectional.

4. The amplifier of claim 3 , wherein the control input of the first protection transistor and a control input of the second protection transistor are biased by a common bias voltage from the voltage source.

5. The amplifier of claim 4 , wherein the common bias voltage is configured to change based on at least one of a voltage of the control input of the first input transistor or a voltage of the control input of the second input transistor.

6. The amplifier of claim 3 , wherein the first input transistor and the second input transistor are p-type metal-oxide-semiconductor (PMOS) transistors each having a gate corresponding to the control input, and the first protection transistor and the second protection transistor are n-type metal-oxide-semiconductor (NMOS) transistors.

7. The amplifier of claim 1 , wherein the voltage clamp includes a first clamping circuit having a first terminal connected to the control input of the first input transistor and a second terminal connected to the control input of the second input transistor, and a second clamping circuit having a first terminal connected to the control input of the second input transistor and a second terminal connected to the control input of the first input transistor.

8. The amplifier of claim 7 , wherein the first clamping circuit and the second clamping circuit each include at least one diode.

9. The amplifier of claim 1 , further comprising input chopping switches interposed between the pair of input terminals and the differential pair of input transistors.

10. The amplifier of claim 1 , wherein the amplifier includes an input stage in cascade with an output stage, wherein the input stage includes the differential pair of input transistors.

11. The amplifier of claim 1 , wherein the voltage clamp comprises a first diode having an anode directly connected to the control input of the first input transistor and a cathode directly connected to the control input of the second input transistor.

12. The amplifier of claim 11 , wherein the voltage clamp further comprises a second diode having an anode directly connected to the control input of the second input transistor and a cathode directly connected to the control input of the first input transistor.

13. The amplifier of claim 12 , wherein the second diode comprises one of a p-n junction diode, a Zener diode, or a Schottky diode.

14. The amplifier of claim 11 , wherein the first diode comprises one of a p-n junction diode, a Zener diode, or a Schottky diode.

15. The amplifier of claim 1 , wherein the voltage clamp comprises at least one of a p-n junction diode, a Zener diode, or a Schottky diode connected between the control input of the first input transistor and the control input of the second input transistor.

16. A method of amplifier input-overvoltage protection with low leakage current, the method comprising:

receiving a differential input signal between a first input terminal and a second input terminal of an amplifier;

amplifying the differential input signal using a differential pair of input transistors of the amplifier, the differential pair of input transistors including a first input transistor and a second input transistor connected at a tail node; and

protecting the differential pair of input transistors from overvoltage, including controlling an impedance between the first input terminal and a control input of the first input transistor using a first protection transistor, providing a bias voltage using a voltage source connected between the tail node and a control input of the first protection transistor, generating a bias current using a current source including a first terminal directly connected to the tail node, and providing clamping between the control input of the first input transistor and a control input of the second input transistor using a voltage clamp.

17. The method of claim 16 , wherein controlling the impedance between the first input terminal and the control input of the first input transistor comprises increasing a channel resistance of the first protection transistor in response to an excursion in a voltage of the first or second input terminal.

18. The method of claim 16 , further comprising controlling an impedance between the second input terminal and a control input of the second input transistor using a second protection transistor, and biasing a control input of the second protection transistor using the bias voltage.

19. The method of claim 18 , further comprising changing a voltage level of the bias voltage based on at least one of a voltage of the control input of the first input transistor and a voltage of the control input of the second input transistor.

20. The method of claim 18 , wherein the voltage clamp comprises at least one of a p-n junction diode, a Zener diode, or a Schottky diode connected between the control input of the first input transistor and the control input of the second input transistor.