IP Library Granted Patent US 11,160,162
Granted Patent B1
US 11,160,162 · App. 16/946,615 · Granted Oct 26, 2021

Via-less patterned ground structure common-mode filter

Inventors: Xinzhi Xing (San Jose, CA); Antonio Ciccomancini Scogna (Cupertino, CA); Jack Nguyen (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
H05K1/0218H03H7/427H05K1/115
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Quick Facts
Patent No.
US 11,160,162
App. No.
16/946,615
Granted
Oct 26, 2021
Kind
B1
Abstract

Disclosed herein are multi-layer metal circuits, such as printed circuit boards (PCBs), with single-sided, partially-shielded, or fully-shielded via-less common-mode filters. The multi-layer metal circuits comprise at least one shield layer, at least one signal trace, and at least one reference layer (e.g., ground). The reference layer comprises a pattern of the via-less common-mode filter. The pattern may comprise, for example, a single piece-wise linear segment, or two or more disjoint and non-intersecting segments (which may be strictly linear or piece-wise linear). The reference layer is electrically isolated from the shield layer, and thus the via-less common-mode filters do not require vias. In addition to being used in PCBs, the disclosed multi-layer metal circuits may also be used in other applications, such as integrated circuits (e.g., implemented in semiconductor chips).

Claims (37)

1. A multi-layer metal circuit, comprising:

a shield layer;

a signal trace layer comprising at least one signal trace; and

a ground layer disposed between the shield layer and the signal trace layer, the ground layer comprising a pattern of a via-less common-mode filter.

2. The multi-layer metal circuit recited in claim 1 , wherein the pattern comprises a first section and a second section, the first and second sections being disjoint and non-intersecting.

3. The multi-layer metal circuit recited in claim 2 , wherein:

the first section is a linear segment and the second section is (a) an omega-shaped segment or (b) a U-shaped segment.

4. The multi-layer metal circuit recited in claim 2 , wherein the pattern has a T-shape.

5. The multi-layer metal circuit recited in claim 4 , wherein a length of the via-less common-mode filter is between approximately 2 mm and approximately 7 mm.

6. The multi-layer metal circuit recited in claim 4 , wherein a length of the via-less common-mode filter is between approximately 2.5 mm and approximately 3.5 mm, and a width of the via-less common-mode filter is between approximately 1 mm and approximately 2 mm.

7. The multi-layer metal circuit recited in claim 2 , wherein the pattern further comprises a third section, wherein at least one dimension of the third section is substantially identical to a corresponding dimension of the second section.

8. The multi-layer metal circuit recited in claim 2 , wherein the pattern further comprises a third section, wherein a shape of the third section is substantially identical to a shape of the second section.

9. The multi-layer metal circuit recited in claim 8 , wherein the first section is linear, and the second and third sections are U-shaped.

10. The multi-layer metal circuit recited in claim 1 , wherein the pattern has an L-shape or a rectangular shape.

11. The multi-layer metal circuit recited in claim 1 , wherein the shield layer is a first shield layer, the ground layer is a first ground layer and is disposed on a first side of the signal layer, and further comprising:

a second shield layer; and

a second ground layer disposed between the second shield layer and a second side of the signal trace layer, the second ground layer comprising a mirror image of the pattern.

12. A data storage device comprising the multi-layer metal circuit recited in claim 1 .

13. A method of manufacturing the multi-layer metal circuit recited in claim 1 , the method comprising etching the pattern into the ground layer.

14. A printed circuit board, comprising:

a shield layer;

at least one signal trace;

a reference layer disposed between the shield layer and the at least one signal trace; and

a common-mode filter etched into the reference layer,

wherein the common-mode filter is electrically isolated from the shield layer.

15. The printed circuit board recited in claim 14 , wherein the common-mode filter comprises a plurality of segments.

16. The printed circuit board recited in claim 15 , wherein the plurality of segments comprises at least one piece-wise linear segment.

17. The printed circuit board recited in claim 16 , wherein the plurality of segments further comprises at least one linear segment.

18. The printed circuit board recited in claim 15 , wherein the plurality of segments comprises a first segment and a second segment, wherein the first and second segments are substantially identical.

19. The printed circuit board recited in claim 15 , wherein the plurality of segments comprises a first segment and a second segment, wherein at least one dimension of the first segment differs from a corresponding dimension of the second segment.

20. The printed circuit board recited in claim 14 , wherein the common-mode filter comprises at least one piece-wise linear segment.

21. A data storage device comprising the printed circuit board recited in claim 14 .

22. A method of manufacturing the printed circuit board recited in claim 14 , the method comprising:

fabricating the shield layer;

fabricating the reference layer;

etching the common-mode filter into the reference layer; and

fabricating the at least one signal trace.

Assignments (5)
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2020
From: XING, XINZHI; SCOGNA, ANTONIO CICCOMANCINI; NGUYEN, JACK
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053289/0509 →
Cited By (1)
US 12,560,985