Efficient packet queueing for computer networks

1. A method comprising:

during a first cycle:

receiving, at a first port of a device, a plurality of network packets;

storing, by the device, at least some portion of a first packet of the plurality of network packets at a first address within a first record bank;

storing, by the device and concurrent with storing the at least some portion of the first packet from the first address, at least some portion of a second packet of the plurality of network packets at a second address within a second record bank, different than the first record bank;

storing, by the device, the first address within the first record bank and the second address within the second record bank in the first link stash associated with the first record bank;

updating, by the device, a tail pointer to reference the second address; and

evicting, by the device, the first link stash associated with the first record bank, including invalidating the first link stash and storing the first address within the first record bank and the second address within the second record bank in a first link bank associated with the first record bank at the first address.

2. The method of claim 1 , further comprising:

during the first cycle:

obtaining a head address from a head pointer, wherein the head address is the first address;

reading the at least some portion of the first packet from the first address concurrent with storing the at least some portion of the first packet from the first address; and

updating the head address of the head pointer to reference the second address within the second record bank.

3. The method of claim 1 , wherein the second address is obtained from the first link stash in accordance with a determination that the first link stash is valid and a determination that the first address of the link stash is the same as the head address obtained from the head pointer.

4. The method of claim 1 , wherein the second address is obtained from the first address of a first link bank associated with the first record bank in accordance with a determination that the first link stash is not valid or a determination that the first address of the link stash is not the same as the head address obtained from the head pointer.

5. The method of claim 1 , further comprising deallocating memory at the first address within the first record bank.

6. The method of claim 1 , further comprising deallocating memory corresponding to the first address within a first link bank associated with the first record bank.

7. The method of claim 1 , further comprising:

during a second cycle:

receiving, at the first port of the device, a second plurality of network packets;

storing, by the device, at least some portion of a third packet of the second plurality of network packets at a third address within a third record bank;

storing, by the device, the second address within the second record bank and the third address within the third record bank in a second link stash associated with the second record bank;

evicting, by the device, a third link stash associated with the third record bank;

storing, by the device and concurrent with storing the at least some portion of the third packet, at least some portion of a fourth packet of the second plurality of network packets at a fourth address within a fourth record bank, different than the third record bank;

storing, by the device, the third address within the third record bank and the fourth address within the fourth record bank in the third link stash;

evicting, by the device, a fourth link stash associated with the fourth record bank; and

updating, by the device, the tail pointer to reference the fourth address.

8. The method of claim 1 , further comprising evicting, by the device, a second link stash associated with the second record bank in response to a determination that the second link stash is valid.

9. The method of claim 1 , wherein the tail pointer, first address, and the second address are globally addressed pointers.

10. The method of claim 1 , wherein each of the link stashes are implemented using single entry flops.

11. The method of claim 1 , wherein each of the record banks are implemented using single-port static random-access memories (SRAMs).

12. A device comprising:

memory; and

processing circuitry having access to the memory and configured to, during a first cycle:

receive a plurality of network packets;

store at least some portion of a first packet of the plurality of network packets at a first address within a first record bank;

store, concurrent with storing the at least some portion of the first packet from the first address, at least some portion of a second packet of the plurality of network packets at a second address within a second record bank, different than the first record bank;

store the first address within the first record bank and the second address within the second record bank in the first link stash associated with the first record bank;

update a tail pointer to reference the second address; and

evict the first link stash associated with the first record bank, including invalidating the first link stash and storing the first address within the first record bank and the second address within the second record bank in a first link bank associated with the first record bank at the first address.

13. The device of claim 12 , the processing circuitry further configured to, during the first cycle:

obtain a head address from a head pointer, wherein the head address is the first address;

read the at least some portion of the first packet from the first address concurrent with storing the at least some portion of the first packet from the first address; and

update the head address of the head pointer to reference the second address within the second record bank.

14. The device of claim 12 , wherein the second address is obtained from the first link stash in accordance with a determination that the first link stash is valid and a determination that the first address of the link stash is the same as the head address obtained from the head pointer.

15. The device of claim 12 , wherein the second address is obtained from the first address of a first link bank associated with the first record bank in accordance with a determination that the first link stash is not valid or a determination that the first address of the link stash is not the same as the head address obtained from the head pointer.

16. The device of claim 12 , the processing circuitry further configured to deallocate memory at the first address within the first record bank.

17. The device of claim 12 , the processing circuitry further configured to deallocate memory corresponding to the first address within a first link bank associated with the first record bank.

18. The device of claim 12 , the processing circuitry further configured to, during a second cycle:

receive, at the first port of the device, a second plurality of network packets;

store, by the device, at least some portion of a third packet of the second plurality of network packets at a third address within a third record bank;

store, by the device, the second address within the second record bank and the third address within the third record bank in a second link stash associated with the second record bank;

evict, by the device, a third link stash associated with the third record bank;

store, by the device and concurrent with storing the at least some portion of the third packet, at least some portion of a fourth packet of the second plurality of network packets at a fourth address within a fourth record bank, different than the third record bank;

store, by the device, the third address within the third record bank and the fourth address within the fourth record bank in the third link stash;

evict, by the device, a fourth link stash associated with the fourth record bank; and

update, by the device, the tail pointer to reference the fourth address.

19. The device of claim 12 , the processing circuitry further configured to:

evict, by the device, a second link stash associated with the second record bank in response to a determination that the second link stash is valid.

20. The device of claim 12 , wherein the tail pointer, first address, and the second address are globally addressed pointers.

21. The device of claim 12 , wherein each of the link stashes are implemented using single entry flops.

22. The device of claim 12 , wherein each of the record banks are implemented using single-port static random-access memories (SRAMs).

23. A non-transitory computer-readable storage medium comprising instructions that, when executed, configure processing circuitry of a device to, during a first cycle:

receive a plurality of network packets;

store at least some portion of a first packet of the plurality of network packets at a first address within a first record bank;

store, concurrent with storing the at least some portion of the first packet from the first address, at least some portion of a second packet of the plurality of network packets at a second address within a second record bank, different than the first record bank;

store the first address within the first record bank and the second address within the second record bank in the first link stash associated with the first record bank;

update a tail pointer to reference the second address; and

evict the first link stash associated with the first record bank, including invalidating the first link stash and storing the first address within the first record bank and the second address within the second record bank in a first link bank associated with the first record bank at the first address.

24. The non-transitory computer-readable storage medium of claim 23 , the processing circuitry further configured to, during the first cycle:

obtain a head address from a head pointer, wherein the head address is the first address;

read the at least some portion of the first packet from the first address concurrent with storing the at least some portion of the first packet from the first address; and

update the head address of the head pointer to reference the second address within the second record bank.

25. The non-transitory computer-readable storage medium of claim 23 , wherein the second address is obtained from the first link stash in accordance with a determination that the first link stash is valid and a determination that the first address of the link stash is the same as the head address obtained from the head pointer.

26. The non-transitory computer-readable storage medium of claim 23 , wherein the second address is obtained from the first address of a first link bank associated with the first record bank in accordance with a determination that the first link stash is not valid or a determination that the first address of the link stash is not the same as the head address obtained from the head pointer.

27. The non-transitory computer-readable storage medium of claim 23 , the processing circuitry further configured to deallocate memory at the first address within the first record bank.

28. The non-transitory computer-readable storage medium of claim 23 , the processing circuitry further configured to deallocate memory corresponding to the first address within a first link bank associated with the first record bank.

29. The non-transitory computer-readable storage medium of claim 23 , the processing circuitry further configured to, during a second cycle:

receive, at the first port of the device, a second plurality of network packets;

store, by the device, at least some portion of a third packet of the second plurality of network packets at a third address within a third record bank;

store, by the device, the second address within the second record bank and the third address within the third record bank in a second link stash associated with the second record bank;

evict, by the device, a third link stash associated with the third record bank;

store, by the device and concurrent with storing the at least some portion of the third packet, at least some portion of a fourth packet of the second plurality of network packets at a fourth address within a fourth record bank, different than the third record bank;

store, by the device, the third address within the third record bank and the fourth address within the fourth record bank in the third link stash;

evict, by the device, a fourth link stash associated with the fourth record bank; and

update, by the device, the tail pointer to reference the fourth address.

30. The non-transitory computer-readable storage medium of claim 23 , the processing circuitry further configured to evict, by the device, a second link stash associated with the second record bank in response to a determination that the second link stash is valid.

31. The non-transitory computer-readable storage medium of claim 23 , wherein the tail pointer, first address, and the second address are globally addressed pointers.

32. The non-transitory computer-readable storage medium of claim 23 , wherein each of the link stashes are implemented using single entry flops.

33. The non-transitory computer-readable storage medium of claim 23 , wherein each of the record banks are implemented using single-port static random-access memories (SRAMs).