Method for power brake staggering and in-rush smoothing for multiple endpoints
Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.
1. A system for controlling power to multiple endpoints, the system comprising:
a baseboard management controller (BMC) comprising a set of BMC instructions to:
identify a set of risers subject to a power brake event;
determine an order for releasing power to each riser of the set of risers; and
communicate the order to a complex programmable logic device (CPLD), the CPLD configurable to communicate a first signal to assert a power brake event and communicate a second signal to de-assert the power brake event; and
a microcontroller unit (MCU) on a riser of the set of risers, the MCU comprising:
a MCU processor; and
a set of MCU instructions executable by the MCU processor to:
communicate with the BMC to determine a source connector instance identifier for the riser;
determine a riser offset time for the riser based on the source connector instance identifier for the riser; and
in response to receiving the first signal from the CPLD to assert the power brake event, throttle power to a set of slots on the riser;
in response to receiving the second signal from the CPLD to de-assert the power brake event, release power to the set of slots on the riser based on the riser offset time.
2. The system of claim 1 , wherein the riser comprises:
a first slot configured to receive power with no delay when power is released to the riser; and
a second slot with a delay circuit configured to delay power to the second slot when power is released to the riser.
3. The system of claim 2 , wherein the delay circuit comprises:
a resistor-capacitor (RC) delay circuit configured to delay power supply to the second slot; and
a Schmitt trigger buffer located between the RC delay circuit and the second slot.
4. The system of claim 3 , wherein one or more of the resistor and the capacitor is configured to minimize a discharge of the capacitor when a power brake event is asserted.
5. The system of claim 1 , wherein the riser comprises one of a fixed riser or a floating riser.
6. The system of claim 1 , wherein:
the CPLD is configured to communicate with the MCU using a one-wire signal; and
the MCU instructions are executable by the MCU processor to:
monitor one-wire signals communicated by the CPLD;
assert a power brake event on the riser when the one-wire signal comprises a first voltage; and
de-assert the power brake event on the riser when the one-wire signal comprises a second voltage greater than the first voltage.
7. The system of claim 1 , wherein the BMC is configured to:
determine a source connector instance identifier for each riser of the set of risers; and
communicate the source connector instance identifier to the MCU.
8. The system of claim 1 , wherein the BMC is configured to:
determine a cable connection number for each riser of the set of risers; and
communicate the cable connection number to the MCU.
9. An information handling system, comprising:
a baseboard management controller (BMC) comprising a set of BMC instructions to:
identify a set of risers subject to a power brake event;
determine an order for releasing power to each riser of the set of risers; and
communicate the order to a complex programmable logic device (CPLD) having a set of CPLD instructions to communicate a first signal to the set of risers to assert a power brake event and communicate a second signal to the set of risers to de-assert the power brake event; and
a microcontroller unit (MCU) on a riser of the set of risers, wherein the MCU is configured to;
communicate with the BMC to determine the order that power will be released to the riser;
determine a riser offset time for the riser based on the order that power will be released to the riser; and
in response to receiving the first signal from the CPLD to assert the power brake event, throttle power to a set of slots on the riser; and
in response to receiving the second signal from the CPLD to de-assert the power brake event, release power to the set of slots on the riser based on the riser offset time.
10. The information handling system of claim 9 , wherein the riser comprises:
a first slot configured to receive power with no delay when power is released to the riser; and
a second slot coupled to a delay circuit configured to delay the release of power to the second slot when power is released to the riser.
11. The information handling system of claim 10 , wherein the delay circuit comprises:
a resistor-capacitor (RC) delay circuit configured to delay the release of power to the second slot; and
a Schmitt trigger buffer located between the RC delay circuit and the second slot.
12. The information handling system of claim 11 , wherein one or more of the resistor and the capacitor is configured to minimize a discharge of the capacitor when a power brake event is asserted.
13. The information handling system of claim 9 , wherein the riser comprises one of a fixed riser or a floating riser.
14. The information handling system of claim 9 , wherein:
the CPLD is configured to communicate with the MCU using a one-wire signal; and
the MCU instructions are executable by the MCU processor to:
monitor one-wire signals communicated by the CPLD;
assert a power brake event on the riser when the one-wire signal comprises a first voltage; and
de-assert the power brake event on the riser when the one-wire signal comprises a second voltage greater than the first voltage.
15. The information handling system of claim 9 , wherein the BMC is configured to:
determine a source connector instance identifier for each riser of the set of risers; and
communicate the source connector instance identifier to the MCU.
16. The information handling system of claim 9 , wherein the BMC is configured to:
determine a cable connection number for each riser of the set of risers; and
communicate the cable connection number to the MCU.
17. A method for releasing multiple endpoints from a power brake event, the method comprising:
determining, by a baseboard management controller (BMC), a set of risers receiving power in an information handling system;
determining a source connector instance identifier for each riser of the set of risers;
determining a set of slots on each riser;
calculating an offset time for each slot based on the source connector instance of the riser and the number of slots on the riser; and
communicating, to a microcontroller unit (MCU) on a riser, the offset time for each slot based on the source connector instance identifier and the number of slots on the riser, wherein
in response to receiving a first signal from a complex programmable logic device (CPLD) to assert the power brake event, the MCU throttling power to the set of slots; and
in response to receiving a second signal from the CPLD to de-assert the power brake event, the MCU releasing power to each slot of the set of slots based on the offset time for the slot.
18. The method of claim 17 , wherein:
a first riser comprises a first set of slots and a first MCU;
the first MCU is configured to perform:
determining a quantity of slots on the first riser subject to the power brake event;
calculating a riser offset time for the first riser based on the number of slots on the first riser and a time period allotted to release power individually to each slot; and
communicating the riser offset time for the first riser to the BMC;
the BMC is configured to perform:
receiving the riser offset time for the first riser; and
communicating the riser offset time to a second MCU on a second riser; and
the second MCU is configured to perform:
receiving the riser offset time from the CPLD; and
calculating an offset time for each slot on the second riser based on the source connector instance of the second riser and the number of slots on the second riser.
19. The method of claim 17 , comprising:
communicating, by the CPLD, the first signal with a first voltage over a one-wire channel;
communicating, by the CPLD, the second signal with a second voltage greater than the first voltage over the one-wire channel.
20. The method of claim 17 , wherein determining the set of risers receiving power in the information handling system and determining the set of slots on each riser are performed during one of a power on self-test (POST) process or a boot process.