IP Library Granted Patent US 11,728,620
Granted Patent B2
US 11,728,620 · App. 16/956,156 · Granted Aug 15, 2023

Semiconductor devices and methods for producing the same

Inventors: Chuni Ghosh (West Windsor, NJ); Guoyang Xu (Mercerville, NJ); Qing Wang (Singapore, SG)
Assignee: Princeton Optronics, Inc.
H01S5/0421H01S5/0201H01S5/023H01S5/0236H01S5/04254H01S5/18305H01S5/3406H01S5/423H01L2224/02165H01L2224/05557H01S5/0237H01S5/04252
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Quick Facts
Patent No.
US 11,728,620
App. No.
16/956,156
Granted
Aug 15, 2023
Kind
B2
Abstract

Semiconductor devices, such as vertical-cavity surface-emitting lasers, and methods for manufacturing the same, are disclosed. The semiconductor devices include contact extensions and electrically conductive adhesive material, such as fusible metal alloys or electrically conductive composites. In some instances, the semiconductor devices further include structured contacts. These components enable the production of semiconductor devices having minimal distortion. For example, arrays of vertical-cavity surface-emitting lasers can be produced exhibiting little to no bowing. Semiconductor devices having minimal distortion exhibit enhanced performance in some instances.

Claims (20)

1. A semiconductor device comprising:

a substrate having first and second opposing sides;

an epitaxial layer having first and second opposing sides, the first side of the epitaxial layer abutting the first side of the substrate;

a substrate contact abutting the second side of the substrate;

an epitaxial contact abutting the second side of the epitaxial layer;

a submount mounted to a submount contact with an electrically conductive material, the submount contact being either the epitaxial contact or the substrate contact;

an obverse submount contact, the obverse submount contact being either the epitaxial contact or the substrate contact that is not associated with the submount contact; and

a contact extension abutting the obverse submount contact,

wherein the contact extension is operable to counteract intrinsic stresses within a vicinity of the first side of the substrate and the first side of the epitaxial layer such that the semiconductor device adopts a form that is substantially planar above the melting temperature of the electrically conductive material, and wherein intrinsic stresses within the contact extension are induced by various processing parameters and tailored to counteract said intrinsic stresses within the vicinity of the first side of the substrate and the first side of the epitaxial layer.

2. The semiconductor device of claim 1 further including a structured extension abutting the submount contact.

3. The semiconductor device of claim 1 , wherein the contact extension is composed of the same material as the obverse submount contact, and the contact extension is characterized by a substantially similar microstructure as the obverse submount contact.

4. The semiconductor device of claim 1 , wherein the contact extension is composed of an electrically conducting metal, optionally wherein the electrically conducting metal includes an element selected from the group consisting of gold, copper, silver, aluminum, platinum, palladium, rhodium, indium, iridium, gallium, bismuth, antimony and tin.

5. The semiconductor device of claim 1 , wherein the electrically conductive material includes a fusible metal alloy or an electrically conductive composite.

6. The semiconductor device of claim 1 , wherein the obverse submount contact is composed of an electrically conducting metal, wherein the electrically conducting metal includes an element selected from the group consisting of gold, copper, silver, aluminum, platinum, palladium, rhodium, indium, iridium, gallium, bismuth, antimony and tin.

7. The semiconductor device of claim 3 , wherein the structured extension includes crenelated extensions configured to increase the contact area between the structured extension and the electrically conductive material.

8. The semiconductor device of claim 1 , wherein the semiconductor device is a vertical-cavity surface-emitting laser.

9. The semiconductor device of claim 8 , wherein the epitaxial layer includes a distributed Bragg reflector and an active region, and the substrate, epitaxial layer, epitaxial contact, substrate contact and submount are operable to generate light.

10. The semiconductor device of claim 8 , wherein the vertical-cavity surface-emitting laser is either:

a top-emitting vertical-cavity surface-emitting laser; or

a bottom-emitting vertical-cavity surface-emitting laser.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2024
From: PRINCETON OPTOTRONICS, INC.
To: AMS-OSRAM INTERNATIONAL GMBH
Reel/Frame 068035/0435 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2020
From: GHOSH, CHUNI; XU, GUOYANG; WANG, QING
To: PRINCETON OPTRONICS, INC.
Reel/Frame 053488/0571 →
Continuity (2)
Provisional Application 62610652 · Dec 27, 2017
Related Publication 20210119414A1 · Apr 22, 2021