Fluid ejection devices including a first memory and a second memory

1. An integrated circuit to drive a plurality of fluid actuation devices, the integrated circuit comprising:

an ID line;

a plurality of first data lines;

a second data line;

a first memory element to be enabled in response to first data on the plurality of first data lines;

a second memory element to be enabled in response to second data on the second data line and a first logic level on the ID line;

a fire line electrically coupled to the second memory element;

a first transistor to enable the second memory element in response to the second data on the second data line and the first logic level on the ID line; and

a second transistor between the fire line and the second memory element to enable the second memory element in response to the first logic level on the ID line.

2. The integrated circuit of claim 1 , further comprising:

a shift register decoder to enable the first memory element in response to the first data on the plurality of first data lines.

3. The integrated circuit of claim 1 ,

wherein the first memory element is accessed via the ID line with the first memory element enabled.

4. The integrated circuit of claim 3 , further comprising:

a fluid actuation device enabled in response to a second logic level on the ID line.

5. The integrated circuit of claim 1 , wherein the first memory element comprises a non-volatile memory element and the second memory element comprises a non-volatile memory element.

6. An integrated circuit to drive a plurality of fluid actuation devices, the integrated circuit comprising:

an ID line;

a first select line;

a second select line;

a first memory element enabled in response to a first logic level on the first select line;

a second memory element enabled in response to a first logic level on the second select line and a first logic level on the ID line;

a fire line electrically coupled to the second memory element;

a first transistor to enable the second memory element in response to the first logic level on the second select line and the first logic level on the ID line; and

a second transistor between the fire line and the second memory element to enable the second memory element in response to the first logic level on the ID line.

7. The integrated circuit of claim 6 ,

wherein the first memory element is accessed via the ID line with the first memory element enabled, and

wherein the second memory element is accessed via the fire line with the second memory element enabled.

8. The integrated circuit of claim 6 , further comprising:

a fluid actuation device enabled in response to a first logic level on the second select line and a second logic level on the ID line.

9. The integrated circuit of claim 8 ,

wherein the fire line is electrically coupled to the second memory element and the fluid actuation device,

wherein the first memory element is accessed via the ID line with the first memory element enabled,

wherein the second memory element is accessed via the fire line with the second memory element enabled; and

wherein the fluid actuation device is activated via the fire line with the fluid actuation device enabled.

10. The integrated circuit of claim 6 , further comprising:

a plurality of first data lines; and

a second data line,

wherein the first memory element is enabled in response to first data on the plurality of first data lines and a first logic level on the first select line, and

wherein the second memory element is enabled in response to second data on the second data line, a first logic level on the second select line, and a first logic level on the ID line.

11. The integrated circuit of claim 6 , wherein the first memory element comprises an erasable programmable read-only memory element and the second memory element comprises a programmable fuse.

12. A method for accessing a first memory and a second memory of a fluid ejection device, the method comprising:

generating a signal on an ID line;

sequentially generating a first select signal and a second select signal;

enabling a first memory element in response to the first select signal and first data on a plurality of first data lines; and

enabling a second memory element in response to the second select signal and second data on a second data line,

wherein enabling the second memory element comprises enabling the second memory element via a first transistor in response to the second select signal, the second data on the second data line, and a first logic level on the ID line and via a second transistor between a fire line and the second memory element in response to the first logic level on the ID line.

13. The method of claim 12 , further comprising:

generating an address signal,

wherein enabling the second memory element comprises enabling the second memory element in response to the second select signal, the second data on the second data line, and the address signal.

14. The method of claim 12 , further comprising:

enabling a fluid actuation device in response to the second select signal and a first second logic level on the ID line.

15. The method of claim 14 , further comprising:

accessing the first memory element via the ID line with the first memory element enabled; and

accessing the second memory element via the fire line with the second memory element enabled.