Verification-processing device, logic-generating device, and verification-processing method

1. A verification-processing device comprising:

an acquisition unit that is configured to acquire a circuit logic model represented by an evaluation expression represented by a logical expression taking, as variables, variables corresponding to a relay, an element, and a connection line that form a relay logic circuit of a verification target, the evaluation expression including at least the logical expression for a case where a failure event occurs in the relay logic circuit; and

a determination unit that is configured to determine a logical state of an output of the relay when a failure event occurs in the element or the connection line, based on the circuit logic model.

2. The verification-processing device according to claim 1 ,

wherein in the variables of the logical expression, conductive states of an element and a connection line on a path of the verification target are indicated by positive logic, and the logical expression when the failure event occurs includes a logical expression that indicates an AND operation of a variable indicating the element on the path of the verification target and a variable indicating the connection line on the path of the verification target.

3. The verification-processing device according to claim 1 ,

wherein the evaluation expression of the relay included in the relay logic circuit of the verification target is described such that an operation result of the evaluation expression of the relay is a value of the variable of the relay.

4. The verification-processing device according to claim 3 ,

wherein in the variables of the logical expression, conductive states of an element and a connection line on a path of the verification target are indicated by positive logic, and

wherein the evaluation expression of the relay includes:

a first expression and a second expression; and

an OR operation of the first expression and the second expression,

wherein the first expression includes an AND operation of a variable indicating the element and a variable indicating the connection line on the path provided with the relay, and

wherein the second expression uses elements and connection lines of the path provided with the relay as analysis targets, the elements being at a point where a short circuit can occur on the path or the elements being on a path between connection lines and the relay, and includes an AND operation of variables indicating the elements which are the analysis targets and variables indicating the connection lines which are the analysis targets.

5. The verification-processing device according to claim 4 ,

wherein the path provided with the relay is a path formed so as to be connectable between a power supply line to which a control voltage of the relay is applied and a ground electrode for the power supply line.

6. The verification-processing device according to claim 1 , further comprising:

a logic generation unit that is configured to generate the circuit logic model, based on an element list which associates the element and the connection line with each other and which stores data related to an element or a connection line connected to a first end of the element or the connection line and an element or a connection line connected to a second end of the element or the connection line.

7. The verification-processing device according to claim 6 ,

wherein the logic generation unit generates the circuit logic model, based on a power supply definition table that stores data indicating a relationship between a connection point of a power supply line to which a control voltage of the relay is applied and a power supply related to the power supply line.

8. A logic-generating device for determining a logical state of an output of a verification target using the verification-processing device according to claim 1 , comprising:

a logic generation unit that is configured to generate the circuit logic model represented by the evaluation expression based on data on a list showing a mutual connection relationship between the element and the connection line, the evaluation expression being represented by a logical expression taking, as variables, the relay, the element, and the connection line that form the relay logic circuit of the verification target, the evaluation expression including at least the logical expression for a case where the failure event occurs in the relay logic circuit.

9. A verification-processing method comprising the steps of:

acquiring a circuit logic model represented by an evaluation expression represented by a logical expression taking as variables, variables corresponding to a relay, an element, and a connection line that form a relay logic circuit of a verification target, the evaluation expression including at least the logical expression for a case where a failure event occurs in the relay logic circuit; and

determining a logical state of an output of the relay when a failure event occurs in the element or the connection line, based on the circuit logic model.