Method for electrochemically etching a semiconductor structure

1. A method for porosifying a semiconductor structure comprising a sub-surface quantum structure of a first III-V semiconductor material, beneath a surface layer of a second III-V semiconductor material having a charge carrier density of less than 5×10 17 cm −3 , the method comprising the steps of:

exposing the surface layer to an electrolyte; and

applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically porosify the sub-surface quantum structure to form a plurality of nanostructures by electrochemical etching through the surface layer, while the surface layer is not porosified.

2. The method according to claim 1 , in which the sub-surface quantum structure comprises a quantum well, or a quantum wire, or a quantum dot, and/or in which the plurality of nanostructures are three-dimensional nanostructures.

3. The method according to claim 1 , in which the sub-surface quantum structure has one or more dimensions of less than or equal to 0.25 nm, or 0.5 nm, or 1 nm, or 2 nm, or 3 nm, or 5 nm, or 8 nm, or 10 nm, or 12 nm, and/or in which the sub-surface quantum structure has a minimum lateral dimension which is at least 5 times, or 10 times, or 50 times, or 100 times greater than a thickness of the sub-surface quantum structure.

4. The method according to claim 1 , in which the semiconductor structure additionally comprises a further sub-surface structure of a third III-V semiconductor material having a charge carrier density of greater than 1×10 17 cm −3 .

5. The method according to claim 1 , in which the sub-surface quantum structure of the first III-V semiconductor material has an electronic bandgap which is narrower than an electronic bandgap of semiconductor material adjacent to it in the semiconductor structure.

6. The method according to claim 1 , in which one or more of the first III-V semiconductor material or the second III-V semiconductor material comprise III-nitride semiconductor materials.

7. The method according to claim 1 , in which the sub-surface quantum structure has a charge carrier density greater than 1×10 17 cm −3 , or greater than 5×10 17 cm −3 , or in which the sub-surface quantum structure is undoped.

8. The method according to claim 1 , in which both the surface layer and the sub-surface quantum structure have a threading dislocation density of at least 1×10 4 cm −2 , 1×10 5 cm −2 , 1×10 6 cm −2 , 1×10 7 cm −2 , or 1×10 8 cm −2 and/or less than 1×10 9 cm −2 or 1×10 10 cm −2 .

9. The method according to claim 1 , in which a thickness of the surface layer is at least 40 nm, or 50 nm, or 100 nm, or 500 nm, and/or less than 1 μm, or 5 μm, or 10 μm.

10. The method according to claim 1 , in which an outer surface of the surface layer has a minimum lateral dimension of at least 300 μm, or at least 500 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm, and/or in which the sub-surface quantum structure has a minimum lateral dimension of at least 300 μm, or at least 500 μm, or at least 1 mm, or at least 10 mm, or at least 5 centimetres.

11. The method according to claim 1 , in which the sub-surface quantum structure of the semiconductor structure comprises a plurality of sub-surface quantum structures formed from the first III-V semiconductor material.

12. The method according to claim 1 , in which the semiconductor structure is provided as a wafer with a diameter of 1 inch (2.54 cm), or 2 inches (5.08 cm), or 6 inches (15.24 cm), or 8 inches (20.36 cm).

13. The method according to claim 1 , in which the semiconductor structure is not pre-patterned with trenches, or in which the semiconductor structure is not pre-patterned with trenches separated by less than 1 cm, or 5 mm, or 1 mm, or 600 μm, or 400 μm, or 200 μm.

14. The method according to claim 1 , in which the surface layer is not coated with an electrically insulating layer or other protective layer during the electrochemical etching, and/or in which the semiconductor structure is not illuminated by light having energy exceeding an electronic bandgap energy of the sub-surface quantum structure material during the electrochemical etching, or in which the semiconductor structure is not illuminated by a light source with a bandwidth of less than 20 nm, or less than 10 nm, or less than 5 nm during the electrochemical etching.

15. The method according to claim 1 , in which the semiconductor structure is an LED structure, comprising a layer of p-type III-V semiconductor material arranged between the surface layer and the sub-surface quantum structure, and a layer of n-type III-V semiconductor material arranged beneath the sub-surface quantum structure.

16. A method for making an LED according to the method of claim 1 , in which the semiconductor structure is an LED semiconductor structure.

17. The method according to claim 4 , in which the sub-surface quantum structure is arranged between the surface layer and the further sub-surface structure of the third III-V material.

18. The method according to claim 4 , in which the further sub-surface structure of the third III-V semiconductor material is a second sub-surface quantum structure.

19. The method according to claim 4 , in which the charge carrier density of the third III-V semiconductor material is at least 5 times, or 10 times, or 100 times, or 1000 times, or 10,000 times, or 100,000 times, or 1,000,000 times higher than the charge carrier density in the surface layer.

20. The method according to claim 6 , in which the III-nitride semiconductor materials are selected from the list consisting of: GaN, InN, AlGaN, InGaN, InAlN and AlInGaN.

21. The method according to claim 11 , in which the semiconductor structure comprises a multiple quantum well (MQW) comprising a plurality of sub-surface quantum well layers arranged in a stack, and separated by intermediate barrier layers of III-V semiconductor material, in which an electronic bandgap of the plurality of sub-surface quantum wells is smaller than a bandgap of the intermediate barrier layers.

22. The method according to claim 21 , in which the plurality of sub-surface quantum wells is sequentially porosified from the surface layer down.

23. The method according to claim 22 , further comprising controlling a porosity of a selected sub-surface quantum well by controlling a potential difference between the electrolyte and the selected sub-surface quantum well during the electrochemical etching.