Method for designing an application task architecture of an electronic control unit with one or more virtual cores

1. A method for designing an application task architecture for an electronic control unit based on an operating system adaptable to operate on a plurality of microcontrollers that each comprise plural cores as processing members configured to work in parallel for executing tasks of the operating system, a basic software layer of the application task architecture configured to connect with a selected microcontroller of the plurality of microcontrollers that forms part of the electronic control unit, the tasks of the operating system to be executed by the electronic control unit being allocated by the application task architecture to at least one of the cores of the selected microcontroller, the method comprising:

developing the application task architecture to use one or more virtual cores, different from the cores of the selected microcontroller, each one of the tasks of the operating system being assigned to said one or more virtual cores; and

associating each one of said one or more virtual cores with one core of the cores of the selected microcontroller, so that for each one of said one or more virtual cores, the tasks of the operating system assigned thereto are allocated to the one core associated with the one of said one or more virtual cores,

wherein at least one core among the cores of the selected microcontroller is determined to have a characteristic, of a set of characteristics defining core capabilities, different from that of an other one of the cores of the selected microcontroller,

wherein each of the characteristics is defined by an order of priority relative to other ones of said characteristics, and

wherein said associating of the one or more virtual cores is based on the characteristics of the cores and the priorities associated with the characteristics.

2. The design method as claimed in claim 1 , wherein the application task architecture uses at least two virtual cores, and each one of said at least two virtual cores is associated with one of the cores of the selected microcontroller.

3. The design method as claimed in claim 2 ,

wherein the cores of the selected microcontroller are arranged in at least two separate groups of cores connected by a bridge, and

wherein a group of virtual cores is produced for each group of the at least two separate groups of cores of the microcontroller, the groups of virtual cores being independent of one another.

4. The design method as claimed in claim 2 , wherein the at least one core among the cores of the selected microcontroller is a checker core having secure and non-secure portions.

5. The design method as claimed in claim 1 , wherein the at least one core among the cores of the selected microcontroller is a checker core having secure and non-secure portions.

6. The design method as claimed in claim 1 , wherein the one or more characteristics comprise i) a capability to carry out a control through redundant execution of software, ii) a security level, iii) a capability to start up the selected microcontroller, and iv) a capability to access input and output peripherals of the selected microcontroller.

7. A method for integrating a multicore microcontroller into an electronic control unit controlled by an operating system adaptable to operate on a plurality of microcontrollers that each comprise plural cores as processing members configured to work in parallel for executing tasks of the operating system, a basic software layer of the application task architecture configured to connect with the multicore microcontroller, the tasks of the operating system to be executed by the electronic control unit being allocated by the application task architecture to at least one of the cores of the multicore microcontroller, the method comprising:

developing the application task architecture by using plural virtual cores, different from the cores of the multicore microcontroller, each one of the tasks of the operating system being assigned to a virtual core of said virtual cores;

determining, for each core among the cores of the multicore microcontroller, a characteristic from a set of characteristics including i) a capability to carry out a control through redundant execution of software, ii) a security level, iii) a capability to start up the multicore microcontroller, and iv) a capability to access input and output peripherals of the multicore microcontroller, where each one of said characteristics has a priority associated therewith; and

associating each core among the cores of the multicore microcontroller with one correspondent virtual core of the virtual cores,

wherein at least one core among the cores of the multicore microcontroller is determined to have one or more of said characteristics different from an other one among the cores of the multicore microcontroller, and

wherein said associating of each core among the cores of the multicore microcontroller is based on the one or more different characteristics of the cores of the multicore microcontroller and based on the priorities associated with the different characteristics.

8. The integration method as claimed in claim 7 , wherein in said associating of each core among the cores of the multicore microcontroller based on the different characteristics of the cores of the multicore microcontroller, the capability to carry out the control through redundant execution of software is considered at a higher priority than all others of said characteristics.

9. The integration method as claimed in claim 8 , further comprising:

establishing a core affinity for at least one virtual core of the virtual cores and for at least one core of the cores of the multicore microcontroller,

wherein the core affinity is defined as any one of i) an integration onto a core of the multicore microcontroller, ii) an integration onto a virtual core, iii) an integration onto a same core of the multicore microcontroller as a given task, iv) an integration onto a core of the multicore microcontroller that operates as a checker core, v) an integration onto a core of the multicore microcontroller that operates as a preferred core for access to peripherals, and vi) an integration onto a core of the multicore microcontroller that operates at a given level of security.

10. The integration method as claimed in claim 7 , further comprising:

establishing a core affinity for at least one virtual core of the virtual cores and for at least one core of the cores of the multicore microcontroller,

wherein the core affinity is defined as any one of i) an integration onto a core of the multicore microcontroller, ii) an integration onto a virtual core, iii) an integration onto a same core of the multicore microcontroller as a given task, iv) an integration onto a core of the multicore microcontroller that operates as a checker core, v) an integration onto a core of the multicore microcontroller that operates as a preferred core for access to peripherals, and vi) an integration onto a core of the multicore microcontroller that operates at a given level of security.

11. An electronic control unit, comprising:

a microcontroller equipped with plural processor cores,

the microcontroller controlled by an operating system that includes an application software layer, a basic software layer, and an application task architecture integrated into the application software layer, the basic software layer being used to connect with the microcontroller,

the application task architecture of the operating system configured to allocate tasks of the operating system to the processor cores of the microcontroller,

wherein the application task architecture of the electronic control unit is configured to implement one or more virtual cores, different from the processor cores of the microcontroller, each one of the tasks of the operating system being assigned to said one or more virtual cores,

wherein the application task architecture associates each one of said one or more virtual cores with one core of the processor cores of the microcontroller, so that for each one of said one or more virtual cores, the tasks of the operating system assigned thereto are allocated to the one core associated with the one of said one or more virtual cores,

wherein at least one processor core among the processor cores of the microcontroller has a characteristic, of a set of characteristics defining core capabilities, different from that of an other one of the processor cores of the microcontroller,

wherein each of the characteristics is defined by an order of priority relative to other ones of said characteristics, and

wherein the one or more virtual cores is associated with the at least one processor core among the processor cores based on the characteristics of the at least one processor core among the processor cores and the priorities associated with the characteristics.

12. The electronic control unit as claimed in claim 11 , wherein the microcontroller comprises three processor cores.

13. A motor vehicle comprising at least one electronic control unit as claimed in claim 11 .

14. The electronic control unit as claimed in claim 11 , wherein the one or more characteristics comprise i) a capability to carry out a control through redundant execution of software, ii) a security level, iii) a capability to start up the microcontroller, and iv) a capability to access input and output peripherals of the microcontroller.

15. The electronic control unit as claimed in claim 11 , wherein the at least one processor core among the processor cores of the microcontroller is a checker core having secure and non-secure portions.