Semiconductor device
A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a first layer in contact with the first electrodes of the semiconductor element and a second layer located on a side opposite to the first electrodes, an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer, and the second layer is spaced apart from the first electrodes of the semiconductor element.
1. A semiconductor device, comprising:
a mounting board; and
a semiconductor element disposed on the mounting board via a metal bump, wherein the semiconductor element includes a semiconductor stacked structure and a first electrode,
the mounting board includes a second electrode,
the first electrode includes a stacked structure including a barrier electrode,
the metal bump disposed at a position where the metal bump overlaps the barrier electrode in a thickness direction is a member integrated in a single piece, the single piece including a first layer in contact with the first electrode, a second layer located on a side of the metal bump opposite to the first electrode, and a transition region located between the first layer and the second layer, an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer,
an average crystal grain size in the transition region approaches from the average crystal grain size of the first layer to the average crystal grain size of the second layer,
a thickness of the transition region is equal to or greater than the average crystal grain size of the second layer,
the average crystal grain size of the first layer is equal to or greater than the thickness of the transition region, and
the second layer is spaced apart from the first electrode.
2. The semiconductor device according to claim 1 , wherein
a width of a first bonding portion which is a bonding portion between the first layer in contact with the first electrode and the first electrode is longer than S/H,
where S denotes a cross-sectional area of the metal bump and H denotes a height of the metal bump in a cross-section of the semiconductor element, the mounting board, and the metal bump in a direction perpendicular to the mounting board.
3. The semiconductor device according to claim 2 , wherein
the second layer has a width shorter than the S/H.
4. The semiconductor device according to claim 1 , wherein
the semiconductor stacked structure includes:
a substrate; and
a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, which are sequentially stacked in order from a side of the substrate.
5. The semiconductor device according to claim 4 , wherein
the first electrode is disposed in contact with the second conductive type semiconductor layer and include a metal film that reflects light from the active layer.
6. The semiconductor device according to claim 1 , wherein
the first layer has a thickness of at least 1 μm.
7. The semiconductor device according to claim 1 , wherein
the barrier electrode comprises Ti.
8. The semiconductor device according to claim 1 , wherein
the mounting board includes a ceramic substrate comprising a sintered body of AlN.
9. A semiconductor device, comprising:
a mounting board; and
a semiconductor element disposed on the mounting board via a metal bump, wherein the semiconductor element includes a semiconductor stacked structure and first electrode, the mounting board includes a second electrode,
the first electrode includes a stacked structure including:
a surface layer comprising gold in contact with the metal bump; and
a barrier electrode,
the metal bump disposed at a position where the metal bump overlap the barrier electrode in a thickness direction is a member integrated in a single piece, the single piece including a first layer in contact with the first electrode, a second layer located on a side of the metal bump opposite to the first electrode, and a transition region located between the first layer and the second layer,
an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer,
an average crystal grain size in the transition region approaches from the average crystal grain size of the first layer to the average crystal grain size of the second layer,
a thickness of the transition region is equal to or greater than the average crystal grain size of the second layer,
the average crystal grain size of the first layer is equal to or greater than the thickness of the transition region, and
a relational expression of C>Rz/2+1−A*B/8 is satisfied,
where A denotes a thickness of the surface layer,
B denotes an average crystal grain size of the surface layer,
C denotes a thickness of the first layer, and
Rz denotes a thickness of the transition region.
10. A method for manufacturing a semiconductor device, comprising:
preparing a semiconductor element including a semiconductor stacked structure and a first electrode, the first electrode including a stacked structure including a barrier electrode, the semiconductor element including a metal bump at a position where the metal bump overlaps the barrier electrode in a thickness direction; and a mounting board including a second electrode;
annealing the metal bump from a side of the first electrode; and
bonding the semiconductor element and the mounting board via the metal bump and the second electrode after the annealing; wherein
an average crystal grain size of crystals included in a first layer in contact with the first electrode becomes larger than an average crystal grain size of crystals included in a second layer located on a side of the metal bump opposite to the first electrode by the annealing in the metal bump.
11. The method for manufacturing the semiconductor device according to claim 10 , wherein
a transition region is formed between the first layer and the second layer in the annealing, and
an average crystal grain size in the transition region approaches from the average crystal grain size of the first layer to the average crystal grain size of the second layer.