Clockless time-to-digital converter
Technologies are provided for time-to-digital conversion without reliance on a clocking signal. The technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.
1. A method, comprising:
receiving a pulse signal by a first processing device of multiple processing devices arranged in a sequential order, wherein each processing device of the multiple processing devices operates on the pulse signal and transmits the pulse signal to a next processing device of the multiple processing devices;
determining multiple output signals based on the pulse signal and the sequential order; and
determining, based on the multiple output signals, a digital word comprising multiple bits, wherein the multiple bits correspond to respective ones of the multiple output signals, and wherein a most significant bit of the multiple bits corresponds to the first processing device and a least significant bit of the multiple bits corresponds to a last processing device of the multiple processing devices according to the sequential order.
2. The method of claim 1 , wherein the pulse signal is based on a first pulse signal and a second pulse signal, wherein a leading edge of the pulse signal corresponds to a leading edge of the first pulse signal and a trailing edge of the pulse signal corresponds to a leading edge of the second pulse signal.
3. The method of claim 1 , wherein each processing device of the multiple processing devices comprises a plurality of logic elements in series.
4. The method of claim 1 , further comprising mapping each output signal of the multiple output signals to a region of a time-based chaotic map.
5. The method of claim 4 , wherein the time-based chaotic map is one of a tent map or a Bernoulli shift map.
6. The method of claim 1 , wherein two or more of the multiple processing devices define a reference time interval that is substantially equivalent.
7. The method of claim 1 , wherein two or more of the multiple processing devices have a propagation delay that is substantially equivalent.
8. A method, comprising:
(i). converting separate pulses to an asynchronous digital pulse;
(ii). stretching and folding the asynchronous digital pulse in time;
(iii). determining a binary signal; and
(iv). repeating operation (ii) and operation (iii) at least one time.
9. The method of claim 8 , wherein the asynchronous digital pulse comprises a first pulse of the separated pulses and a second pulse of the separated pulses, and wherein a leading edge of the first pulse corresponds to a leading edge of the asynchronous digital pulse and a leading edge of the second pulse corresponds to a trailing edge of the asynchronous digital pulse.
10. The method of claim 8 , further comprising mapping the binary signal to a region of a time-based chaotic map.
11. The method of claim 8 further comprising, determining, based on the binary signal, a bit of a digital word comprising a plurality of bits.
12. The method of claim 8 , wherein folding the asynchronous digital pulse in time comprises providing the asynchronous digital pulse to a circuit that decreases a length of the asynchronous digital pulse through an operation that relies on a length of an input pulse width.
13. The method of claim 8 , wherein stretching the asynchronous digital pulse in time comprises providing the asynchronous digital pulse to a circuit that increases a length of the asynchronous digital pulse through an operation that relies on a length of an input pulse width.
14. A device, comprising:
processing circuitry; and
storage circuitry having stored thereon processor-executable instructions that, in response to execution by the processing circuitry, cause the device to:
receive input signal by a first component of the processing circuitry, wherein the input signal comprises a first pulse signal and a second pulse signal, and wherein a leading edge of the first pulse signal corresponds to a leading edge of the input signal and a leading edge of the second pulse signal corresponds to a trailing edge of the input signal;
determine multiple output signals based on the input signal and a sequential order of second components of the processing circuitry, wherein the multiple output signals correspond to respective ones of the second components; and
determine, based on the multiple output signals, a digital word comprising multiple bits, wherein a first bit of the multiple bits corresponds to a first output of the multiple output signals and a second bit of the multiple bits corresponds to a second output of the multiple output signals.
15. The device of claim 14 , wherein each output comprises a pulse signal that is stretched and folded in time.
16. The device of claim 14 , further comprising mapping each output signal of the multiple output signals to a region of a time-based chaotic map.
17. The device of claim 16 , wherein the time-based chaotic map is one of a tent map or a Bernoulli shift map.
18. The device of claim 14 , wherein the processing circuitry and the storage circuitry constitute at least one of a field-programmable gate array or an ASIC.
19. The device of claim 14 , wherein the processing circuitry includes a time delay component, and wherein at least one of the processing circuitry or the storage circuitry constitute one of an optical system, an electronic system, an acoustic system, or a hybrid of the foregoing.
20. An apparatus, comprising:
a module for receiving an input signal, wherein the input signal comprises a first pulse signal and a second pulse signal, and wherein a leading edge of the first pulse signal corresponds to a leading edge of the input signal and a leading edge of the second pulse signal corresponds to a trailing edge of the input signal;
a module for determining multiple output signals based on the input signal; and
a module for determining, based on the multiple output signals, a digital word comprising multiple bits, wherein a first bit of the multiple bits corresponds to a first output of the multiple output signals and a second bit of the multiple bits corresponds to a second output of the multiple output signals.