Automatic gain control circuit of transimpedance amplifier

1. An automatic gain control circuit of a transimpedance amplifier, comprising a transimpedance amplifier TIA 1 , a transimpedance amplifier TIA 2 , an NMOS transistor Q 1 , an NMOS transistor Q 2 , an error amplifier U 3 , and a bias current source Ib; the transimpedance amplifier TIA 2 and the transimpedance amplifier TIA 1 having an identical circuit structure, size and process parameter; the NMOS transistor Q 1 and the NMOS transistor Q 2 having an identical turn-on voltage threshold;

an input terminal of the transimpedance amplifier TIA 1 being connected to a drain of the NMOS transistor Q 1 ; an output terminal of the transimpedance amplifier TIA 1 being connected to a source of the NMOS transistor Q 1 ;

an input terminal of the transimpedance amplifier TIA 2 being connected to a drain of the NMOS transistor Q 2 ; an output terminal of the transimpedance amplifier TIA 2 being connected to a source of the NMOS transistor Q 2 ;

a positive input terminal and a negative input terminal of the error amplifier U 3 being connected to the input terminal and the output terminal of the transimpedance amplifier TIA 2 , respectively; an output terminal of the error amplifier U 3 being connected to a gate of the NMOS transistor Q 1 and a gate of the NMOS transistor Q 2 ;

an input terminal of the bias current source Ib being connected to a working power supply VDD, an output terminal of the bias current source Ib being connected to the positive input terminal of the error amplifier U 3 and the drain of the MOS transistor Q 2 .

2. The automatic gain control circuit of the transimpedance amplifier as claimed in claim 1 , wherein the transimpedance amplifier TIA 1 includes an inverting amplifier U 1 and a resistor R 1 ; the transimpedance amplifier TIA 2 includes an inverting amplifier U 2 and a resistor R 2 ;

an input terminal and an output terminal of the inverting amplifier U 1 are connected to two ends of the resistor R 1 , respectively; the input terminal of the inverting amplifier U 1 serves as the input terminal of the transimpedance amplifier TIA 1 , the output terminal of the inverting amplifier U 1 serves as the output terminal of the transimpedance amplifier TIA 1 ;

an input terminal and an output terminal of the inverting amplifier U 2 are connected to two ends of the resistor R 2 , respectively; the input terminal of the inverting amplifier U 2 serves as the input terminal of the transimpedance amplifier TIA 2 , the output terminal of the inverting amplifier U 2 serves as the output terminal of the transimpedance amplifier TIA 2 .

3. The automatic gain control circuit of the transimpedance amplifier as claimed in claim 2 , wherein the inverting amplifier U 1 includes a resistor R 01 , an NMOS transistor M 1 , and an NMOS transistor M 2 ;

a gate of the NMOS transistor M 2 serves as the input terminal of the inverting amplifier U 1 ; a source of the NMOS transistor M 2 is grounded, a drain of the NMOS transistor M 2 is connected to a source of the NMOS transistor M 1 , a gate of the NMOS transistor M 1 is connected to a bias power supply Vb, a drain of the NMOS transistor M 1 serves as the output terminal of the inverting amplifier U 1 , the drain of the NMOS transistor M 1 is connected to one end of the resistor R 01 , another end of the resistor R 01 is connected to the working power supply VDD; the inverting amplifier U 2 includes a resistor R 02 , an NMOS transistor M 3 , and an NMOS transistor M 4 ; the NMOS transistor M 3 and the NMOS transistor M 1 have an identical turn-on voltage threshold; the NMOS transistor M 4 and the NMOS transistor M 2 have an identical turn-on voltage threshold; the resistor R 02 and the resistor R 01 have an identical resistance;

a gate of the NMOS transistor M 4 serves as the input terminal of the inverting amplifier U 2 ; a source of the NMOS transistor M 4 is grounded, a drain of the NMOS transistor M 4 is connected to a source of the NMOS transistor M 3 , a gate of the NMOS transistor M 3 is connected to the bias power supply Vb, a drain of the NMOS transistor M 3 serves as the output terminal of the inverting amplifier U 2 , the drain of the NMOS transistor M 3 is connected to one end of the resistor R 02 , and another end of the resistor R 02 is connected to the working power supply VDD.

4. The automatic gain control circuit of the transimpedance amplifier as claimed in claim 1 , wherein the bias current source Ib has an output current between zero and 1 microampere.