IP Library Granted Patent US 11,194,508
Granted Patent B2
US 11,194,508 · App. 16/977,118 · Granted Dec 7, 2021

Remote input/output system

Inventors: Daichi Motojima (Shinagawa, JP); Motohiko Okabe (Fuchu, JP)
Assignees: KABUSHIKI KAISHA TOSHIBA; TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
G06F3/0656G06F3/061G06F3/067G06F3/0658G06F13/122
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Quick Facts
Patent No.
US 11,194,508
App. No.
16/977,118
Granted
Dec 7, 2021
Kind
B2
Abstract

A remote I/O system includes an information network control module, I/O interface modules, and a remote I/O module. The information network control module includes a common memory and a second control IC. The second control IC includes a variation detecting circuit that includes a data latch buffer that stores read data from an information network; and a variation detection memory that stores data previously read from the information network. The variation detecting circuit compares data stored in the data latch buffer with data stored in the variation detection memory, to detect a variation in the data. The second control IC transmits, to the I/O interface module, by cyclic scan transmission, data from one of the scan memory areas corresponding to the data having the variation detected by the variation detecting circuit.

Claims (23)

1. A remote input/output system comprising:

an information network control module;

a plurality of input/output interface modules; and

a remote input/output module, wherein

the input/output interface modules each comprise:

an input/output interface memory; and

a first control integrated circuit configured to receive data from the information network control module or another I/O interface module by cyclic scan transmission through a remote input/output bus, write the data to the input/output interface memory, and output the data from the input/output interface memory to the remote input/output module,

the information network control module comprises:

a common memory including scan memory areas individually provided for the input/output interface modules; and

a second control integrated circuit configured to read data from an information network, write the data to the scan memory areas, and transmit the data from the scan memory areas to the I/O interface modules by cyclic scan transmission through the remote I/O bus,

the second control integrated circuit comprises a variation detecting circuit including:

a data latch buffer that stores the data read from the information network; and

a variation detection memory that stores data previously read from the information network,

the variation detecting circuit compares the data stored in the data latch buffer with the data stored in the variation detection memory, to detect a variation in the data, and

the second control integrated circuit transmits data from one of the scan memory areas to the input/output interface modules by cyclic scan transmission, the data corresponding to the data having the variation detected by the variation detecting circuit.

2. The remote input/output system according to claim 1 , wherein

in response to no stored data in the variation detection memory, the variation detecting circuit executes an initial update process to write the read data from the information network to the variation detection memory, and

in reading data from the information network next after the initial update process, the variation detecting circuit compares the data stored in the data latch buffer with the data stored in the variation detection memory, to detect a variation in the data.

3. The remote input/output system according to claim 2 , wherein

the second control integrated circuit comprises a ring buffer that stores the data read from the information network, and

before execution of the initial update process, the second control integrated circuit transmits the data from the ring buffer to the input/output interface modules by cyclic scan transmission.

4. The remote input/output system according to claim 1 , wherein

after receipt of an instruction for execution of cyclic scan transmission from an external CPU module, the variation detecting circuit compares the data stored in the data latch buffer with the data stored in the variation detection memory in a preset cycle, to detect a variation in the data.

Assignments (2)
MERGER Recorded Jul 29, 2025
From: TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 072239/0263 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2020
From: MOTOJIMA, DAICHI; OKABE, MOTOHIKO
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
Reel/Frame 053653/0683 →
Priority Claims (1)
JP JP2019-022830 · Feb 12, 2019 · national
Continuity (1)
Related Publication 20200409593A1 · Dec 31, 2020