Method and circuit for protecting a DRAM memory device from the row hammer effect

1. A method of protecting a DRAM memory device from a row hammer effect, the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one prevention logic configured to respectively define sub-banks as contiguous sections of rows of a bank, each sub-bank being associated with an activation threshold, and to execute, at each activation of a row of a given sub-bank of the sub-banks of the memory device, a step of incrementing an activation counter associated with the given sub-bank and determination of a required number of preventive refreshes of this of the given sub-bank;

the prevention logic also being configured to execute a preventive refresh sequence comprising:

a step of identifying a need for preventive refresh of a determined sub-bank of the sub-banks of the memory device based on one or more characteristics related to the sub-banks;

a step of triggering an operation to refresh a current index row associated with the determined sub-bank;

a step of incrementing the current index row associated with the determined sub-bank;

decrementation of the required number of preventive refreshments of this of the determined sub-bank;

wherein the operation to refresh the current index row is forming a step of a preventive refresh cycle leading to refresh at least all the rows of the determined sub-bank; and wherein the activation threshold of the determined sub-bank is chosen so that a complete preventive refresh cycle of the determined sub-bank is carried out before the number of rows activated in the determined sub-bank exceeds a critical hammer value.

2. The protection method of claim 1 , in which the required number of preventive refreshes of each given sub-bank is stored in a data structure.

3. The protection method of claim 2 , in which the step of identifying a need for preventive refresh of a determined sub-bank comprises browsing the data structure to identify the determined sub-bank whose required number of preventive refreshes is greater than or equal to 1.

4. The protection method of claim 1 , in which the determination of the required number of preventive refreshes comprises the incrementing of a pending refresh counter, the preventive refresh sequence comprises a step of decrementing the refresh counter, and the preventive refresh sequence is executed repeatedly as long as the pending refresh counter exceeds a floor value.

5. The protection method of claim 2 , in which an index of a given sub-bank is inserted into a list of sub-banks awaiting refresh when the required number of preventive refreshes of the given sub-bank reaches the value 1.

6. The protection method of claim 5 , in which the list is formed by chaining between them entries of the data structure.

7. The protection method of claim 5 , in which the step of identifying a need for preventive refresh of a determined sub-bank consists in identifying that the list of sub-banks awaiting refresh is not empty.

8. The protection method of claim 5 , in which the index of a given sub-bank is removed from the list when the required number of preventive refreshes of the given sub-bank goes under the value 1.

9. The protection method of claim 2 , in which the required number of preventive refreshes of all the sub-banks is less than 1, and the step of identifying a need for preventive refresh of the determined sub-bank comprises identification, in the data structure, of the determined sub-bank whose activation counter is maximum and resetting of the activation counter following the triggering of the operation to refresh.

10. The protection method of claim 1 , in which the step of identifying a need for preventive refresh of a determined sub-bank is executed at the end of the step of incrementing the activation counter of a given sub-bank, and comprises a comparison of the required number of preventive refresh of the given sub-bank with a determined threshold.

11. The protection method of claim 1 , in which preparation of an operation to refresh a current index row comprises its storage in a buffer memory.

12. The protection method of claim 1 , in which the determination of a required number of preventive refreshes comprises:

a step of incrementing, modulo the activation threshold, the activation counter of the given sub-bank;

incrementation of the required number of preventive refreshes of the given sub-bank, if the incrementation modulo the activation threshold has reset the activation counter of the given sub-bank to zero.

13. The protection method of claim 12 , in which the activation counter is incremented by a parameter strictly less than the activation threshold.

14. The protection method of claim 1 , in which the preventive refresh cycle also leads to refresh the rows of the lower margin and/or the higher margin of the determined sub-bank.

15. The protection method of claim 1 , wherein the activated row of the given sub-bank is one of the first rows, or respectively one of the last rows, of the given sub-bank and the incrementation step also comprises the incrementation of the activation counter associated with a lower sub-bank, or respectively associated with an upper sub-bank.

16. The protection method of claim 1 , in which the activation threshold of a sub-bank is variable with temperature, supply voltage, frequency of the activations of a sub-bank, or the memory characteristics.

17. The protection method of claim 1 , in which the activation threshold is distinct from one sub-bank to another.

18. The protection method of claim 1 , in which the step of triggering an operation to refresh a current index row comprises insertion of a preventive refresh request in a control traffic intended for a memory bank in which the determined sub-bank resides.

19. The protection method of claim 1 , in which the complete preventive refresh cycle of the determined sub-bank leads to refresh certain rows of the determined sub-bank a plurality of times.

20. The protection method of claim 1 , in which the activation threshold defines a variable progress coefficient during a complete cycle of preventive refresh of the determined sub-bank.

21. The protection method of claim 1 , in which the prevention logic is associated with a plurality of banks.

22. A DRAM memory device, buffer circuit or controller of a DRAM memory device comprising row hammer effect prevention logic configured to implement a protection method according to claim 1 .

23. A DRAM memory device, buffer circuit or a controller of a DRAM memory device according to claim 22 , in which the DRAM memory device comprises at least one integrated processor.

24. A DRAM memory device, buffer circuit or controller of a DRAM memory device according to claim 22 , wherein the DRAM memory device comprises a plurality of replacement blocks, the replacement blocks being separated from each other by any means preventing a row of a block from being replacement of attacking by hammer a row of another replacement block.

25. A DRAM memory device, buffer circuit or controller of a DRAM memory device according to claim 24 , in which the rows of a replacement block are intended to replace defective rows of a single sub-bank.

26. A DRAM memory device, buffer circuit or controller of a DRAM memory device according to claim 24 , in which the rows of a replacement block are intended to replace defective rows of a plurality of sub-banks, the rows composing the replacement block being all part of the preventive refresh cycle of the sub-banks sharing the replacement block.

27. A DRAM memory device, buffer circuit or controller of a DRAM memory device according to claim 24 , in which the replacement block is a sub-bank.

28. A DRAM memory device, buffer circuit or controller of a DRAM memory device according to claim 22 , in which the DRAM sub-banks comprise replacement rows, and these replacement rows being part of the preventive refresh cycle of the sub-banks.