High density IC capacitor structure
High density integrated circuit (IC) capacitor structures and fabrication methods that increase the capacitive density of integrated capacitors with little or no reduction in Q-factor by using a stacked high-density integrated capacitor structure that includes substrate-contact (“S-contact”) capacitor plates. Embodiments include a plurality of S-contact plates fabricated in electrical connection with a capacitor formed in a metal interconnect layer. Some embodiments include interstitial S-contact plates to provide additional capacitive density. Embodiments may also utilize single-layer transfer (SLT) and double-layer transfer (DLT) techniques to create ICs with high density, high Q-factor capacitors. Such capacitors can be beneficially combined with other structures made possible in SLT and DLT IC structures, such as metal interconnect layer capacitors and inductors, and one or more FETs having a conductive aligned supplemental gate. Embodiments are compatible with fabrication of CMOS SOI transistors, and are particularly suitable for radio frequency and analog applications.
1. A method for fabrication of an integrated circuit, including:
(a) forming a buried-oxide (BOX) layer proximate a substrate;
(b) forming a fabrication region proximate the BOX layer;
(c) forming a region of interlayer dielectric proximate the BOX layer;
(d) forming at least one metal interconnect layer proximate the region of interlayer dielectric;
(e) forming at least one lateral capacitor from a portion of at least one of the at least one metal interconnect layer; and
(f) forming a plurality of substrate-contact (S-contact) plates in electrical contact with at least one of the at least one lateral capacitor and configured to increase the capacitive density of the at least one of the at least one lateral capacitor.
2. The method of claim 1 , wherein the S-contact plates penetrate through the fabrication region and the BOX layer to the substrate.
3. The method of claim 1 , wherein the S-contact plates penetrate through the fabrication region and partially penetrate the BOX layer.
4. The method of claim 1 , wherein at least one lateral capacitor includes first and second lateral interdigitated structures.
5. The method of claim 1 , wherein at least one lateral capacitor structure includes a plurality of stacked lateral capacitors each comprising first and second interdigitated structures.
6. The method of claim 1 , wherein at least one lateral capacitor includes positive and negative interdigitated structures each having at least one finger, each finger aligned with and in electrical contract with a corresponding one of the plurality of S-contact plates.
7. The method of claim 1 , wherein at least one capacitor includes first and second lateral interdigitated structures each having at least one finger, each finger aligned with and in electrical contract with a corresponding one of the plurality of S-contact plates, and further including positioning at least one interstitial S-contact plate between adjacent fingers.
8. The method of claim 1 , further including forming at least one field effect transistor formed on and/or in the fabrication region.
9. The method of claim 1 , further including forming at least one field effect transistor having a conductive aligned supplemental gate.
10. The method of claim 1 , further including:
(a) forming a redistribution layer; and
(b) forming at least one additional capacitor and/or inductor from a portion of the at least one metal interconnect layer and a portion of the redistribution layer.
11. The method of claim 1 , further including forming at least one inductor from a portion of the at least one metal interconnect layer.
12. The method of claim 1 , further including forming the S-contact plates of a low resistivity conductive material.