Memory system and non-transitory computer readable recording medium

1. A memory system comprising:

a nonvolatile memory which comprises a plurality of memory block groups, the plurality of memory block groups including first plural memory blocks, second plural memory blocks, and plural input memory blocks corresponding to the first and second plural memory blocks; and

a controller which controls the nonvolatile memory and comprises a memory and a buffer memory, wherein

the memory stores management data including a first relationship between the first and second plural memory blocks and the plural input memory blocks, and a second relationship between blocks included in the nonvolatile memory and the plurality of memory block groups, and

the controller receives, from a host device, a write command, identification data corresponding to the first plural memory blocks, a logical address, and write data corresponding to the identification data,

associates the logical address of the write data with the identification data and a physical address which indicates a position of the write data in the nonvolatile memory,

writes, based on the management data, the write data corresponding to the identification data to the buffer memory, then writes the write data corresponding to the identification data in the buffer memory to one of the plural input memory blocks, and then writes valid data corresponding to the identification data in the one of the plural input memory blocks to one of the first plural memory blocks corresponding to the identification data,

observes data storage conditions of the plural input memory blocks, the first plural memory blocks, and the second plural memory blocks,

changes the second relationship based on the data storage conditions, and

updates the management data based on a result of changing the second relationship.

2. The memory system according to claim 1 , wherein the controller generates the management data further including a relationship between data stored in the plural input memory blocks and the first plural memory blocks or the second plural memory blocks.

3. The memory system according to claim 1 , wherein

the controller acquires a data amount of data stored in the plural input memory blocks and corresponding to the first plural memory blocks,

subtracts the acquired data amount from a predetermined data amount corresponding to the first plural memory blocks, and

assigns at least one block to the first plural memory blocks based on a value obtained from the subtraction, and updates the management data based on a result of the assigning.

4. The memory system according to claim 3 , wherein

the controller generates the management data further including a relationship between the first plural memory blocks and the acquired data amount, and

when the valid data stored in a block which is a data transfer source within the plural input memory blocks and corresponding to the first plural memory blocks is transferred to the first plural memory blocks, the controller subtracts a data amount of the valid data transferred to the first plural memory blocks from the acquired data amount and updates the management data based on the value obtained from the subtraction.

5. The memory system according to claim 1 , wherein the controller selects, from the plural input memory blocks, a block of which write time is oldest as a block which is a data transfer source, and

writes the valid data stored in the block which is the data transfer source to the first plural memory blocks corresponding to the identification data.

6. The memory system according to claim 1 , wherein the controller selects a block of which data amount of the valid data is least from the plural input memory blocks as a block which is a data transfer source, and

writes the valid data stored in the block which is the data transfer source to the first plural memory blocks corresponding to the identification data.

7. The memory system according to claim 1 , wherein the controller selects a block of which data amount of the valid data is less than a threshold value from the plural input memory blocks as a block which is a data transfer source, and writes the valid data stored in the block which is the data transfer source to the first plural memory blocks corresponding to the identification data.

8. The memory system according to claim 1 , wherein the controller reduces the number of blocks included in the plural input memory blocks when a data amount of valid data stored in a block which is a data transfer source within the plural input memory blocks is less than a threshold value, and updates the management data based on a result of the reducing.

9. The memory system according to claim 1 , wherein the controller increases the number of blocks included in the plural input memory blocks when a data amount of valid data stored in a block which is a data transfer source within the plural input memory blocks is more than a threshold value, and updates the management data based on a result of the increasing.

10. The memory system according to claim 1 , wherein

the plurality of memory block groups further comprise third plural memory blocks and fourth plural memory blocks, the plural input memory blocks comprise first plural input memory blocks and second plural input memory blocks, the first plural input memory blocks correspond to the first and second plural memory blocks, the second plural input memory blocks correspond to the third and fourth plural memory blocks,

the first relationship comprises a relationship between the first and second plural memory blocks and the first plural input memory blocks, and a relationship between the third and fourth plural memory blocks and the second plural input memory blocks,

the controller writes, based on the management data, the write data corresponding to the identification data to the buffer memory, then writes the write data corresponding to the identification data in the buffer memory to the first plural input memory blocks, and then writes

valid data corresponding to the identification data in the first plural input memory blocks to the first plural memory blocks corresponding to the identification data, and

the controller observes data storage conditions of the first and second plural input memory blocks and the first to fourth plural memory blocks, and changes the second relationship based on the data storage conditions.

11. The memory system according to claim 1 , wherein

each of the first plural memory blocks, the second plural memory blocks, and the plural input memory blocks comprises a plurality of blocks,

each of the plurality of blocks is an area of a unit of data erase, and comprises a plurality of pages, and each of the plurality of pages is an area of a unit of data write or an area of a unit of data read.

12. The memory system according to claim 1 , wherein

the first plural memory blocks correspond to a first namespace, the second plural memory blocks correspond to a second namespace, and

the plural input memory blocks correspond to an input namespace.

13. The memory system according to claim 10 , wherein

the first plural memory blocks correspond to a first namespace,

the second plural memory blocks correspond to a second namespace,

the first plural input memory blocks correspond to a first input namespace,

the third plural memory blocks correspond to a third namespace,

the fourth plural memory blocks correspond to a fourth namespace, and

the second plural input memory blocks correspond to a second input namespace.

14. The memory system according to claim 1 , wherein the number of blocks included in the first plural memory blocks is different from the number of blocks included in the second plural memory blocks.

15. The memory system according to claim 10 , wherein the number of blocks included in the first plural input memory blocks is different from the number of blocks included in the second plural input memory blocks.

16. The memory system according to claim 1 , wherein

the controller selects the plural input memory blocks assigned to the first plural memory blocks and the second plural memory blocks, from the blocks of the nonvolatile memory.

17. The memory system according to claim 10 , wherein

the controller selects the first plural input memory blocks assigned to the first plural memory blocks and the second plural memory blocks, from the blocks of the nonvolatile memory, and

selects the second plural input memory blocks assigned to the third plural memory blocks and the fourth plural memory blocks, from the blocks of the nonvolatile memory.

18. The memory system according to claim 1 , wherein

the controller stores data of the plural input memory blocks to the first plural memory blocks or the second plural memory blocks subjected to garbage collection, when the garbage collection is performed with respect to the first plural memory blocks or the second plural memory blocks.

19. The memory system according to claim 10 , wherein the controller stores data of the first plural input memory blocks to the first plural memory blocks or the second plural memory blocks subjected to first garbage collection, when the first garbage collection is performed with respect to the first plural memory blocks or the second plural memory blocks, and

stores data of the second plural input memory blocks to the third plural memory blocks or the fourth plural memory blocks subjected to second garbage collection, when the second garbage collection is performed with respect to the third plural memory blocks or the fourth plural memory blocks.

20. A non-transitory computer readable recording medium which stores a program

causing a computer to function as:

a reception unit, an address translation unit, a write unit, and a configuration unit, wherein the computer controls a nonvolatile memory, a memory, and a buffer memory, the nonvolatile memory comprises a plurality of memory block groups, the plurality of memory block groups including first plural memory blocks, second plural memory blocks, and

plural input memory blocks corresponding to the first and second plural memory blocks, the configuration unit stores management data in the memory,

the management data includes a first relationship between the first and second plural memory blocks and the plural input memory blocks, and a second relationship between blocks included in the nonvolatile memory and the plurality of memory block groups, the reception unit receives, from a host device, a write command, identification data corresponding to the first plural memory blocks, a logical address, and write data corresponding to the identification data,

the address translation unit associates the logical address of the write data with the identification data and a physical address which indicates a position of the write data in the nonvolatile memory,

the write unit writes, based on the management data, the write data corresponding to the identification data to the buffer memory, then writes the write data corresponding to the identification data in the buffer memory to one of the plural input memory blocks, and then writes valid data corresponding to the identification data in the one of the plural input memory blocks to one of the first plural memory blocks corresponding to the identification data,

the configuration unit observes data storage conditions of the plural input memory blocks, the first plural memory blocks, and the second plural memory blocks, and changes the second relationship based on the data storage conditions, and

the configuration unit updates the management data based on a result of changing the second relationship.